Commit b1a9557a authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: fulfill powerplay peak profiling mode shader/memory clock settings 



Enable peak profiling mode shader/memory clock reporting for powerplay
framework.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 975b4b1d

drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c

+8 −2
Original line number Diff line number Diff line
@@ -769,10 +769,16 @@ static int pp_dpm_read_sensor(void *handle, int idx, 


	switch (idx) {

	case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:

		*((uint32_t *)value) = hwmgr->pstate_sclk;

		*((uint32_t *)value) = hwmgr->pstate_sclk * 100;

		return 0;

	case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:

		*((uint32_t *)value) = hwmgr->pstate_mclk;

		*((uint32_t *)value) = hwmgr->pstate_mclk * 100;

		return 0;

	case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK:

		*((uint32_t *)value) = hwmgr->pstate_sclk_peak * 100;

		return 0;

	case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK:

		*((uint32_t *)value) = hwmgr->pstate_mclk_peak * 100;

		return 0;

	case AMDGPU_PP_SENSOR_MIN_FAN_RPM:

		*((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

+13 −3
Original line number Diff line number Diff line
@@ -375,6 +375,17 @@ static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr) 
	return 0;

}



static void smu10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)

{

	hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK;

	hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK;



	smum_send_msg_to_smc(hwmgr,

			     PPSMC_MSG_GetMaxGfxclkFrequency,

			     &hwmgr->pstate_sclk_peak);

	hwmgr->pstate_mclk_peak = SMU10_UMD_PSTATE_PEAK_FCLK;

}



static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)

{

	struct amdgpu_device *adev = hwmgr->adev;
@@ -398,6 +409,8 @@ static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 
			return ret;

	}



	smu10_populate_umdpstate_clocks(hwmgr);



	return 0;

}
@@ -574,9 +587,6 @@ static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 


	hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;



	hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;

	hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;



	/* enable the pp_od_clk_voltage sysfs file */

	hwmgr->od_enabled = 1;

	/* disabled fine grain tuning function by default */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

+63 −13
Original line number Diff line number Diff line
@@ -1501,6 +1501,65 @@ static int smu7_populate_edc_leakage_registers(struct pp_hwmgr *hwmgr) 
	return ret;

}



static void smu7_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)

{

	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);

	struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;

	struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk =

			hwmgr->dyn_state.vddc_dependency_on_sclk;

	struct phm_ppt_v1_information *table_info =

			(struct phm_ppt_v1_information *)(hwmgr->pptable);

	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk =

			table_info->vdd_dep_on_sclk;

	int32_t tmp_sclk, count, percentage;



	if (golden_dpm_table->mclk_table.count == 1) {

		percentage = 70;

		hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[0].value;

	} else {

		percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /

				golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;

		hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;

	}



	tmp_sclk = hwmgr->pstate_mclk * percentage / 100;



	if (hwmgr->pp_table_version == PP_TABLE_V0) {

		for (count = vddc_dependency_on_sclk->count - 1; count >= 0; count--) {

			if (tmp_sclk >= vddc_dependency_on_sclk->entries[count].clk) {

				hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[count].clk;

				break;

			}

		}

		if (count < 0)

			hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[0].clk;



		hwmgr->pstate_sclk_peak =

			vddc_dependency_on_sclk->entries[vddc_dependency_on_sclk->count - 1].clk;

	} else if (hwmgr->pp_table_version == PP_TABLE_V1) {

		for (count = vdd_dep_on_sclk->count - 1; count >= 0; count--) {

			if (tmp_sclk >= vdd_dep_on_sclk->entries[count].clk) {

				hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[count].clk;

				break;

			}

		}

		if (count < 0)

			hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[0].clk;



		hwmgr->pstate_sclk_peak =

			vdd_dep_on_sclk->entries[vdd_dep_on_sclk->count - 1].clk;

	}



	hwmgr->pstate_mclk_peak =

		golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;



	/* make sure the output is in Mhz */

	hwmgr->pstate_sclk /= 100;

	hwmgr->pstate_mclk /= 100;

	hwmgr->pstate_sclk_peak /= 100;

	hwmgr->pstate_mclk_peak /= 100;

}



static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)

{

	int tmp_result = 0;
@@ -1625,6 +1684,8 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 
	PP_ASSERT_WITH_CODE((0 == tmp_result),

			"pcie performance request failed!", result = tmp_result);



	smu7_populate_umdpstate_clocks(hwmgr);



	return 0;

}
@@ -3143,15 +3204,12 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le 
		for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;

			count >= 0; count--) {

			if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {

				tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk;

				*sclk_mask = count;

				break;

			}

		}

		if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {

		if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)

			*sclk_mask = 0;

			tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;

		}



		if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)

			*sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
@@ -3161,15 +3219,12 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le 


		for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {

			if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {

				tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk;

				*sclk_mask = count;

				break;

			}

		}

		if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {

		if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)

			*sclk_mask = 0;

			tmp_sclk =  table_info->vdd_dep_on_sclk->entries[0].clk;

		}



		if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)

			*sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
@@ -3181,8 +3236,6 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le 
		*mclk_mask = golden_dpm_table->mclk_table.count - 1;



	*pcie_mask = data->dpm_table.pcie_speed_table.count - 1;

	hwmgr->pstate_sclk = tmp_sclk;

	hwmgr->pstate_mclk = tmp_mclk;



	return 0;

}
@@ -3195,9 +3248,6 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr, 
	uint32_t mclk_mask = 0;

	uint32_t pcie_mask = 0;



	if (hwmgr->pstate_sclk == 0)

		smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);



	switch (level) {

	case AMD_DPM_FORCED_LEVEL_HIGH:

		ret = smu7_force_dpm_highest(hwmgr);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

+14 −2
Original line number Diff line number Diff line
@@ -1016,6 +1016,18 @@ static void smu8_reset_acp_boot_level(struct pp_hwmgr *hwmgr) 
	data->acp_boot_level = 0xff;

}



static void smu8_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)

{

	struct phm_clock_voltage_dependency_table *table =

				hwmgr->dyn_state.vddc_dependency_on_sclk;



	hwmgr->pstate_sclk = table->entries[0].clk / 100;

	hwmgr->pstate_mclk = 0;



	hwmgr->pstate_sclk_peak = table->entries[table->count - 1].clk / 100;

	hwmgr->pstate_mclk_peak = 0;

}



static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr)

{

	smu8_program_voting_clients(hwmgr);
@@ -1024,6 +1036,8 @@ static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 
	smu8_program_bootup_state(hwmgr);

	smu8_reset_acp_boot_level(hwmgr);



	smu8_populate_umdpstate_clocks(hwmgr);



	return 0;

}
@@ -1167,8 +1181,6 @@ static int smu8_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 


	data->sclk_dpm.soft_min_clk = table->entries[0].clk;

	data->sclk_dpm.hard_min_clk = table->entries[0].clk;

	hwmgr->pstate_sclk = table->entries[0].clk;

	hwmgr->pstate_mclk = 0;



	level = smu8_get_max_sclk_level(hwmgr) - 1;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

+26 −5
Original line number Diff line number Diff line
@@ -3008,6 +3008,30 @@ static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool 
	return 0;

}



static void vega10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)

{

	struct phm_ppt_v2_information *table_info =

			(struct phm_ppt_v2_information *)(hwmgr->pptable);



	if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&

	    table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {

		hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;

		hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;

	} else {

		hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;

		hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk;

	}



	hwmgr->pstate_sclk_peak = table_info->vdd_dep_on_sclk->entries[table_info->vdd_dep_on_sclk->count - 1].clk;

	hwmgr->pstate_mclk_peak = table_info->vdd_dep_on_mclk->entries[table_info->vdd_dep_on_mclk->count - 1].clk;



	/* make sure the output is in Mhz */

	hwmgr->pstate_sclk /= 100;

	hwmgr->pstate_mclk /= 100;

	hwmgr->pstate_sclk_peak /= 100;

	hwmgr->pstate_mclk_peak /= 100;

}



static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)

{

	struct vega10_hwmgr *data = hwmgr->backend;
@@ -3082,6 +3106,8 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 
				    result = tmp_result);

	}



	vega10_populate_umdpstate_clocks(hwmgr);



	return result;

}
@@ -4169,8 +4195,6 @@ static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_fo 
		*sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;

		*soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;

		*mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;

		hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;

		hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;

	}



	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
@@ -4281,9 +4305,6 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 
	uint32_t mclk_mask = 0;

	uint32_t soc_mask = 0;



	if (hwmgr->pstate_sclk == 0)

		vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);



	switch (level) {

	case AMD_DPM_FORCED_LEVEL_HIGH:

		ret = vega10_force_dpm_highest(hwmgr);