Unverified Commit b189dde9 authored by Mark Brown's avatar Mark Brown
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Merge series "soundwire/ASoC: abstract platform-dependent bases" from Bard... 

Merge series "soundwire/ASoC: abstract platform-dependent bases" from Bard Liao <yung-chuan.liao@linux.intel.com>:

shim base and alh base are platform-dependent. This series suggests
to use variables for those bases. It allows us to use different bases
for new platforms.

v2:
 - Update the commit message of "soundwire: move intel sdw register
   definitions to sdw_intel.h"

Bard Liao (6):
  soundwire: move intel sdw register definitions to sdw_intel.h
  ASoC: SOF: intel: add sdw_shim/alh_base to sof_intel_dsp_desc
  ASoC: SOF: intel: hda: remove HDA_DSP_REG_SNDW_WAKE_STS definition
  ASoC: SOF: intel: move sof_intel_dsp_desc() forward
  ASoC: SOF: intel: add snd_sof_dsp_check_sdw_irq ops
  soundwire: intel: introduce shim and alh base

 drivers/soundwire/intel.c           | 74 ------------------------
 drivers/soundwire/intel_init.c      | 14 ++---
 include/linux/soundwire/sdw_intel.h | 87 +++++++++++++++++++++++++++++
 sound/soc/sof/intel/cnl.c           |  6 ++
 sound/soc/sof/intel/hda.c           | 39 ++++++++-----
 sound/soc/sof/intel/hda.h           |  8 ++-
 sound/soc/sof/intel/icl.c           |  3 +
 sound/soc/sof/intel/shim.h          |  3 +
 sound/soc/sof/intel/tgl.c           | 12 ++++
 9 files changed, 149 insertions(+), 97 deletions(-)

--
2.17.1
parents 2f535e2c 60e9feb7

drivers/soundwire/intel.c

+0 −74
Original line number Diff line number Diff line
@@ -40,80 +40,6 @@ static int md_flags; 
module_param_named(sdw_md_flags, md_flags, int, 0444);

MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");



/* Intel SHIM Registers Definition */

#define SDW_SHIM_LCAP			0x0

#define SDW_SHIM_LCTL			0x4

#define SDW_SHIM_IPPTR			0x8

#define SDW_SHIM_SYNC			0xC



#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))

#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))

#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))

#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))

#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))

#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))



#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))

#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))

#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))

#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))

#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))



#define SDW_SHIM_WAKEEN			0x190

#define SDW_SHIM_WAKESTS		0x192



#define SDW_SHIM_LCTL_SPA		BIT(0)

#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)

#define SDW_SHIM_LCTL_CPA		BIT(8)

#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)



#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)

#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)

#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)

#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)

#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)

#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)

#define SDW_SHIM_SYNC_SYNCGO		BIT(24)



#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)

#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)

#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)



#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)

#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)

#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)

#define SDW_SHIM_PCMSYCM_DIR		BIT(15)



#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)

#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)

#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)

#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)



#define SDW_SHIM_IOCTL_MIF		BIT(0)

#define SDW_SHIM_IOCTL_CO		BIT(1)

#define SDW_SHIM_IOCTL_COE		BIT(2)

#define SDW_SHIM_IOCTL_DO		BIT(3)

#define SDW_SHIM_IOCTL_DOE		BIT(4)

#define SDW_SHIM_IOCTL_BKE		BIT(5)

#define SDW_SHIM_IOCTL_WPDD		BIT(6)

#define SDW_SHIM_IOCTL_CIBD		BIT(8)

#define SDW_SHIM_IOCTL_DIBD		BIT(9)



#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)

#define SDW_SHIM_CTMCTL_DODS		BIT(1)

#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)



#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)

#define SDW_SHIM_WAKESTS_STATUS		BIT(0)



/* Intel ALH Register definitions */

#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))

#define SDW_ALH_NUM_STREAMS		64



#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3

#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)

#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)



enum intel_pdi_type {

	INTEL_PDI_IN = 0,

	INTEL_PDI_OUT = 1,

drivers/soundwire/intel_init.c

+5 −9
Original line number Diff line number Diff line
@@ -18,12 +18,6 @@ 
#include "cadence_master.h"

#include "intel.h"



#define SDW_SHIM_LCAP		0x0

#define SDW_SHIM_BASE		0x2C000

#define SDW_ALH_BASE		0x2C800

#define SDW_LINK_BASE		0x30000

#define SDW_LINK_SIZE		0x10000



static void intel_link_dev_release(struct device *dev)

{

	struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
@@ -69,8 +63,8 @@ static struct sdw_intel_link_dev *intel_link_dev_register(struct sdw_intel_res * 
	link->mmio_base = res->mmio_base;

	link->registers = res->mmio_base + SDW_LINK_BASE

		+ (SDW_LINK_SIZE * link_id);

	link->shim = res->mmio_base + SDW_SHIM_BASE;

	link->alh = res->mmio_base + SDW_ALH_BASE;

	link->shim = res->mmio_base + res->shim_base;

	link->alh = res->mmio_base + res->alh_base;



	link->ops = res->ops;

	link->dev = res->dev;
@@ -220,6 +214,8 @@ static struct sdw_intel_ctx 
	}



	ctx->mmio_base = res->mmio_base;

	ctx->shim_base = res->shim_base;

	ctx->alh_base = res->alh_base;

	ctx->link_mask = res->link_mask;

	ctx->handle = res->handle;

	mutex_init(&ctx->shim_lock);
@@ -308,7 +304,7 @@ sdw_intel_startup_controller(struct sdw_intel_ctx *ctx) 
		return -EINVAL;



	/* Check SNDWLCAP.LCOUNT */

	caps = ioread32(ctx->mmio_base + SDW_SHIM_BASE + SDW_SHIM_LCAP);

	caps = ioread32(ctx->mmio_base + ctx->shim_base + SDW_SHIM_LCAP);

	caps &= GENMASK(2, 0);



	/* Check HW supported vs property value */

include/linux/soundwire/sdw_intel.h

+87 −0
Original line number Diff line number Diff line
@@ -7,6 +7,85 @@ 
#include <linux/irqreturn.h>

#include <linux/soundwire/sdw.h>



#define SDW_SHIM_BASE			0x2C000

#define SDW_ALH_BASE			0x2C800

#define SDW_LINK_BASE			0x30000

#define SDW_LINK_SIZE			0x10000



/* Intel SHIM Registers Definition */

#define SDW_SHIM_LCAP			0x0

#define SDW_SHIM_LCTL			0x4

#define SDW_SHIM_IPPTR			0x8

#define SDW_SHIM_SYNC			0xC



#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))

#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))

#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))

#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))

#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))

#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))



#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))

#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))

#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))

#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))

#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))



#define SDW_SHIM_WAKEEN			0x190

#define SDW_SHIM_WAKESTS		0x192



#define SDW_SHIM_LCTL_SPA		BIT(0)

#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)

#define SDW_SHIM_LCTL_CPA		BIT(8)

#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)



#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)

#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)

#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)

#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)

#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)

#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)

#define SDW_SHIM_SYNC_SYNCGO		BIT(24)



#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)

#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)

#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)



#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)

#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)

#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)

#define SDW_SHIM_PCMSYCM_DIR		BIT(15)



#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)

#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)

#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)

#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)



#define SDW_SHIM_IOCTL_MIF		BIT(0)

#define SDW_SHIM_IOCTL_CO		BIT(1)

#define SDW_SHIM_IOCTL_COE		BIT(2)

#define SDW_SHIM_IOCTL_DO		BIT(3)

#define SDW_SHIM_IOCTL_DOE		BIT(4)

#define SDW_SHIM_IOCTL_BKE		BIT(5)

#define SDW_SHIM_IOCTL_WPDD		BIT(6)

#define SDW_SHIM_IOCTL_CIBD		BIT(8)

#define SDW_SHIM_IOCTL_DIBD		BIT(9)



#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)

#define SDW_SHIM_CTMCTL_DODS		BIT(1)

#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)



#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)

#define SDW_SHIM_WAKESTS_STATUS		BIT(0)



/* Intel ALH Register definitions */

#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))

#define SDW_ALH_NUM_STREAMS		64



#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3

#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)

#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)



/**

 * struct sdw_intel_stream_params_data: configuration passed during

 * the @params_stream callback, e.g. for interaction with DSP
@@ -116,6 +195,8 @@ struct sdw_intel_slave_id { 
 * @link_list: list to handle interrupts across all links

 * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.

 * @shim_mask: flags to track initialization of SHIM shared registers

 * @shim_base: sdw shim base.

 * @alh_base: sdw alh base.

 */

struct sdw_intel_ctx {

	int count;
@@ -128,6 +209,8 @@ struct sdw_intel_ctx { 
	struct list_head link_list;

	struct mutex shim_lock; /* lock for access to shared SHIM registers */

	u32 shim_mask;

	u32 shim_base;

	u32 alh_base;

};



/**
@@ -146,6 +229,8 @@ struct sdw_intel_ctx { 
 * machine-specific quirks are handled in the DSP driver.

 * @clock_stop_quirks: mask array of possible behaviors requested by the

 * DSP driver. The quirks are common for all links for now.

 * @shim_base: sdw shim base.

 * @alh_base: sdw alh base.

 */

struct sdw_intel_res {

	int count;
@@ -157,6 +242,8 @@ struct sdw_intel_res { 
	struct device *dev;

	u32 link_mask;

	u32 clock_stop_quirks;

	u32 shim_base;

	u32 alh_base;

};



/*

sound/soc/sof/intel/cnl.c

+6 −0
Original line number Diff line number Diff line
@@ -347,6 +347,9 @@ const struct sof_intel_dsp_desc cnl_chip_info = { 
	.rom_init_timeout	= 300,

	.ssp_count = CNL_SSP_COUNT,

	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE,

	.sdw_alh_base = SDW_ALH_BASE,

	.check_sdw_irq	= hda_common_check_sdw_irq,

};

EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
@@ -363,5 +366,8 @@ const struct sof_intel_dsp_desc jsl_chip_info = { 
	.rom_init_timeout	= 300,

	.ssp_count = ICL_SSP_COUNT,

	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE,

	.sdw_alh_base = SDW_ALH_BASE,

	.check_sdw_irq	= hda_common_check_sdw_irq,

};

EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

sound/soc/sof/intel/hda.c

+26 −13
Original line number Diff line number Diff line
@@ -41,6 +41,17 @@ 
#define EXCEPT_MAX_HDR_SIZE	0x400

#define HDA_EXT_ROM_STATUS_SIZE 8



static const struct sof_intel_dsp_desc

	*get_chip_info(struct snd_sof_pdata *pdata)

{

	const struct sof_dev_desc *desc = pdata->desc;

	const struct sof_intel_dsp_desc *chip_info;



	chip_info = desc->chip_info;



	return chip_info;

}



#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)



/*
@@ -155,6 +166,8 @@ static int hda_sdw_probe(struct snd_sof_dev *sdev) 
	memset(&res, 0, sizeof(res));



	res.mmio_base = sdev->bar[HDA_DSP_BAR];

	res.shim_base = hdev->desc->sdw_shim_base;

	res.alh_base = hdev->desc->sdw_alh_base;

	res.irq = sdev->ipc_irq;

	res.handle = hdev->info.handle;

	res.parent = sdev->dev;
@@ -211,7 +224,7 @@ static int hda_sdw_exit(struct snd_sof_dev *sdev) 
	return 0;

}



static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)

bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)

{

	struct sof_intel_hda_dev *hdev;

	bool ret = false;
@@ -237,6 +250,17 @@ static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 
	return ret;

}



static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)

{

	const struct sof_intel_dsp_desc *chip;



	chip = get_chip_info(sdev->pdata);

	if (chip && chip->check_sdw_irq)

		return chip->check_sdw_irq(sdev);



	return false;

}



static irqreturn_t hda_dsp_sdw_thread(int irq, void *context)

{

	return sdw_intel_thread(irq, context);
@@ -249,7 +273,7 @@ static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 
	hdev = sdev->pdata->hw_pdata;

	if (hdev->sdw &&

	    snd_sof_dsp_read(sdev, HDA_DSP_BAR,

			     HDA_DSP_REG_SNDW_WAKE_STS))

			     hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS))

		return true;



	return false;
@@ -668,17 +692,6 @@ static int hda_init_caps(struct snd_sof_dev *sdev) 
	return 0;

}



static const struct sof_intel_dsp_desc

	*get_chip_info(struct snd_sof_pdata *pdata)

{

	const struct sof_dev_desc *desc = pdata->desc;

	const struct sof_intel_dsp_desc *chip_info;



	chip_info = desc->chip_info;



	return chip_info;

}



static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context)

{

	struct snd_sof_dev *sdev = context;