Commit b1880258 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/audio: write audio/video latency info for DCE6/8 



Needed by the hda driver to properly set up synchronization
on the audio side.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
parent 712fd8a2

drivers/gpu/drm/radeon/dce6_afmt.c

+43 −0
Original line number Diff line number Diff line
@@ -102,6 +102,49 @@ void dce6_afmt_select_pin(struct drm_encoder *encoder) 
	       AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));

}



void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,

				    struct drm_display_mode *mode)

{

	struct radeon_device *rdev = encoder->dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	struct drm_connector *connector;

	struct radeon_connector *radeon_connector = NULL;

	u32 tmp = 0, offset;



	if (!dig->afmt->pin)

		return;



	offset = dig->afmt->pin->offset;



	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {

		if (connector->encoder == encoder) {

			radeon_connector = to_radeon_connector(connector);

			break;

		}

	}



	if (!radeon_connector) {

		DRM_ERROR("Couldn't find encoder's connector\n");

		return;

	}



	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {

		if (connector->latency_present[1])

			tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |

				AUDIO_LIPSYNC(connector->audio_latency[1]);

		else

			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);

	} else {

		if (connector->latency_present[0])

			tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |

				AUDIO_LIPSYNC(connector->audio_latency[0]);

		else

			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);

	}

	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);

}



void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)

{

	struct radeon_device *rdev = encoder->dev->dev_private;

drivers/gpu/drm/radeon/evergreen_hdmi.c

+3 −0
Original line number Diff line number Diff line
@@ -35,6 +35,8 @@ 
extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder);

extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder);

extern void dce6_afmt_select_pin(struct drm_encoder *encoder);

extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,

					   struct drm_display_mode *mode);



/*

 * update the N and CTS parameters for a given pixel clock rate
@@ -361,6 +363,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode 
	if (ASIC_IS_DCE6(rdev)) {

		dce6_afmt_select_pin(encoder);

		dce6_afmt_write_sad_regs(encoder);

		dce6_afmt_write_latency_fields(encoder, mode);

	} else {

		evergreen_hdmi_write_sad_regs(encoder);

		dce4_afmt_write_latency_fields(encoder, mode);

drivers/gpu/drm/radeon/sid.h

+45 −0
Original line number Diff line number Diff line
@@ -683,6 +683,51 @@ 
 * bit5 = 176.4 kHz

 * bit6 = 192 kHz

 */



#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC         0x37

#       define VIDEO_LIPSYNC(x)                           (((x) & 0xff) << 0)

#       define AUDIO_LIPSYNC(x)                           (((x) & 0xff) << 8)

/* VIDEO_LIPSYNC, AUDIO_LIPSYNC

 * 0   = invalid

 * x   = legal delay value

 * 255 = sync not supported

 */

#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR             0x38

#       define HBR_CAPABLE                                (1 << 0) /* enabled by default */



#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0               0x3a

#       define MANUFACTURER_ID(x)                        (((x) & 0xffff) << 0)

#       define PRODUCT_ID(x)                             (((x) & 0xffff) << 16)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1               0x3b

#       define SINK_DESCRIPTION_LEN(x)                   (((x) & 0xff) << 0)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2               0x3c

#       define PORT_ID0(x)                               (((x) & 0xffffffff) << 0)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3               0x3d

#       define PORT_ID1(x)                               (((x) & 0xffffffff) << 0)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4               0x3e

#       define DESCRIPTION0(x)                           (((x) & 0xff) << 0)

#       define DESCRIPTION1(x)                           (((x) & 0xff) << 8)

#       define DESCRIPTION2(x)                           (((x) & 0xff) << 16)

#       define DESCRIPTION3(x)                           (((x) & 0xff) << 24)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5               0x3f

#       define DESCRIPTION4(x)                           (((x) & 0xff) << 0)

#       define DESCRIPTION5(x)                           (((x) & 0xff) << 8)

#       define DESCRIPTION6(x)                           (((x) & 0xff) << 16)

#       define DESCRIPTION7(x)                           (((x) & 0xff) << 24)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6               0x40

#       define DESCRIPTION8(x)                           (((x) & 0xff) << 0)

#       define DESCRIPTION9(x)                           (((x) & 0xff) << 8)

#       define DESCRIPTION10(x)                          (((x) & 0xff) << 16)

#       define DESCRIPTION11(x)                          (((x) & 0xff) << 24)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7               0x41

#       define DESCRIPTION12(x)                          (((x) & 0xff) << 0)

#       define DESCRIPTION13(x)                          (((x) & 0xff) << 8)

#       define DESCRIPTION14(x)                          (((x) & 0xff) << 16)

#       define DESCRIPTION15(x)                          (((x) & 0xff) << 24)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8               0x42

#       define DESCRIPTION16(x)                          (((x) & 0xff) << 0)

#       define DESCRIPTION17(x)                          (((x) & 0xff) << 8)



#define AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL          0x54

#       define AUDIO_ENABLED                             (1 << 31)