Commit b166e525 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'timers-v5.18-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core 

Pull clocksource/events updates from Daniel Lezcano:

  - Fix return error code check for the timer-of layer when getting
    the base address (Guillaume Ranquet)

  - Remove MMIO dependency, add notrace annotation for sched_clock
    and increase the timer resolution for the Microchip
    PIT64b (Claudiu Beznea)

  - Convert DT bindings to yaml for the Tegra timer (David Heidelberg)

  - Fix compilation error on architecture other than ARM for the
    i.MX TPM (Nathan Chancellor)

  - Add support for the event stream scaling for 1GHz counter on
    the arch ARM timer (Marc Zyngier)

  - Support a higher number of interrupts by the Exynos MCT timer
    driver (Alim Akhtar)

  - Detect and prevent memory corruption when the specified number
    of interrupts in the DTS is greater than the array size in the
    code for the Exynos MCT timer (Krzysztof Kozlowski)

  - Fix regression from a previous errata fix on the TI DM
    timer (Drew Fustini)

  - Several fixes and code improvements for the i.MX TPM
    driver (Peng Fan)

Link: https://lore.kernel.org/all/a8cd9be9-7d70-80df-2b74-1a8226a215e1@linaro.org
parents 1f1893d7 4467b8ba

Documentation/devicetree/bindings/timer/nvidia,tegra-timer.yaml

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# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: "http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: NVIDIA Tegra timer



maintainers:

  - Stephen Warren <swarren@nvidia.com>



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: nvidia,tegra210-timer

    then:

      properties:

        interrupts:

          # Either a single combined interrupt or up to 14 individual interrupts

          minItems: 1

          maxItems: 14

          description: >

            A list of 14 interrupts; one per each timer channels 0 through 13



  - if:

      properties:

        compatible:

          oneOf:

            - items:

                - enum:

                    - nvidia,tegra114-timer

                    - nvidia,tegra124-timer

                    - nvidia,tegra132-timer

                - const: nvidia,tegra30-timer

            - items:

                - const: nvidia,tegra30-timer

                - const: nvidia,tegra20-timer

    then:

      properties:

        interrupts:

          # Either a single combined interrupt or up to 6 individual interrupts

          minItems: 1

          maxItems: 6

          description: >

            A list of 6 interrupts; one per each of timer channels 1 through 5,

            and one for the shared interrupt for the remaining channels.



  - if:

      properties:

        compatible:

          const: nvidia,tegra20-timer

    then:

      properties:

        interrupts:

          # Either a single combined interrupt or up to 4 individual interrupts

          minItems: 1

          maxItems: 4

          description: |

            A list of 4 interrupts; one per timer channel.



properties:

  compatible:

    oneOf:

      - const: nvidia,tegra210-timer

        description: >

          The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit

          timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived

          from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock

          (TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,

          or watchdog interrupts.

      - items:

          - enum:

              - nvidia,tegra114-timer

              - nvidia,tegra124-timer

              - nvidia,tegra132-timer

          - const: nvidia,tegra30-timer

      - items:

          - const: nvidia,tegra30-timer

          - const: nvidia,tegra20-timer

        description: >

          The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free

          running counter, and 5 watchdog modules. The first two channels may also

          trigger a legacy watchdog reset.

      - const: nvidia,tegra20-timer

        description: >

          The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free

          running counter. The first two channels may also trigger a watchdog reset.



  reg:

    maxItems: 1



  interrupts: true



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: timer





required:

  - compatible

  - reg

  - interrupts

  - clocks



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    timer@60005000 {

        compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";

        reg = <0x60005000 0x400>;

        interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,

                     <0 1 IRQ_TYPE_LEVEL_HIGH>,

                     <0 41 IRQ_TYPE_LEVEL_HIGH>,

                     <0 42 IRQ_TYPE_LEVEL_HIGH>,

                     <0 121 IRQ_TYPE_LEVEL_HIGH>,

                     <0 122 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&tegra_car 214>;

    };

  - |

    #include <dt-bindings/clock/tegra210-car.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>



    timer@60005000 {

        compatible = "nvidia,tegra210-timer";

        reg = <0x60005000 0x400>;

        interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&tegra_car TEGRA210_CLK_TIMER>;

        clock-names = "timer";

    };

Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt

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NVIDIA Tegra20 timer



The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free

running counter. The first two channels may also trigger a watchdog reset.



Required properties:



- compatible : should be "nvidia,tegra20-timer".

- reg : Specifies base physical address and size of the registers.

- interrupts : A list of 4 interrupts; one per timer channel.

- clocks : Must contain one entry, for the module clock.

  See ../clocks/clock-bindings.txt for details.



Example:



timer {

	compatible = "nvidia,tegra20-timer";

	reg = <0x60005000 0x60>;

	interrupts = <0 0 0x04

			0 1 0x04

			0 41 0x04

			0 42 0x04>;

	clocks = <&tegra_car 132>;

};

Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt

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NVIDIA Tegra210 timer



The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit

timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived

from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock

(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,

or watchdog interrupts.



Required properties:

- compatible : "nvidia,tegra210-timer".

- reg : Specifies base physical address and size of the registers.

- interrupts : A list of 14 interrupts; one per each timer channels 0 through

  13.

- clocks : Must contain one entry, for the module clock.

  See ../clocks/clock-bindings.txt for details.



timer@60005000 {

	compatible = "nvidia,tegra210-timer";

	reg = <0x0 0x60005000 0x0 0x400>;

	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&tegra_car TEGRA210_CLK_TIMER>;

	clock-names = "timer";

};

Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt

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NVIDIA Tegra30 timer



The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free

running counter, and 5 watchdog modules. The first two channels may also

trigger a legacy watchdog reset.



Required properties:



- compatible : For Tegra30, must contain "nvidia,tegra30-timer".  Otherwise,

  must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where

  <chip> is tegra124 or tegra132.

- reg : Specifies base physical address and size of the registers.

- interrupts : A list of 6 interrupts; one per each of timer channels 1

    through 5, and one for the shared interrupt for the remaining channels.

- clocks : Must contain one entry, for the module clock.

  See ../clocks/clock-bindings.txt for details.



timer {

	compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";

	reg = <0x60005000 0x400>;

	interrupts = <0 0 0x04

		      0 1 0x04

		      0 41 0x04

		      0 42 0x04

		      0 121 0x04

		      0 122 0x04>;

	clocks = <&tegra_car 214>;

};

arch/arm/boot/dts/dra7-l4.dtsi

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Original line number Diff line number Diff line
@@ -3482,8 +3482,7 @@ 
				ti,timer-pwm;

			};

		};



		target-module@2c000 {			/* 0x4882c000, ap 17 02.0 */

		timer15_target: target-module@2c000 {	/* 0x4882c000, ap 17 02.0 */

			compatible = "ti,sysc-omap4-timer", "ti,sysc";

			reg = <0x2c000 0x4>,

			      <0x2c010 0x4>;
@@ -3511,7 +3510,7 @@ 
			};

		};



		target-module@2e000 {			/* 0x4882e000, ap 19 14.0 */

		timer16_target: target-module@2e000 {	/* 0x4882e000, ap 19 14.0 */

			compatible = "ti,sysc-omap4-timer", "ti,sysc";

			reg = <0x2e000 0x4>,

			      <0x2e010 0x4>;