Commit b14e4f20 authored by Jun Lei's avatar Jun Lei Committed by Alex Deucher
Browse files

drm/amd/display: revert support for DID2.0 dsc passthrough 



3x4K60 displays over MST with DSC enabled was not able to light up
due to this patch.

Signed-off-by: default avatarJun Lei <jun.lei@amd.com>
Reviewed-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarAnson Jacob <Anson.Jacob@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 765ff7ad

drivers/gpu/drm/amd/display/dc/dc_dsc.h

+3 −4
Original line number Diff line number Diff line
@@ -51,7 +51,6 @@ struct dc_dsc_policy { 
	int min_slice_height; // Must not be less than 8

	uint32_t max_target_bpp;

	uint32_t min_target_bpp;

	uint32_t preferred_bpp_x16;

	bool enable_dsc_when_not_needed;

};
@@ -63,8 +62,8 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, 
bool dc_dsc_compute_bandwidth_range(

		const struct display_stream_compressor *dsc,

		uint32_t dsc_min_slice_height_override,

		uint32_t min_bpp_x16,

		uint32_t max_bpp_x16,

		uint32_t min_bpp,

		uint32_t max_bpp,

		const struct dsc_dec_dpcd_caps *dsc_sink_caps,

		const struct dc_crtc_timing *timing,

		struct dc_dsc_bw_range *range);
@@ -79,7 +78,7 @@ bool dc_dsc_compute_config( 
		struct dc_dsc_config *dsc_cfg);



void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,

		uint32_t max_target_bpp_limit_override_x16,

		uint32_t max_target_bpp_limit_override,

		struct dc_dsc_policy *policy);



void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

+0 −1
Original line number Diff line number Diff line
@@ -769,7 +769,6 @@ struct dc_crtc_timing { 
#endif



	struct dc_crtc_timing_flags flags;

	uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */

	struct dc_dsc_config dsc_cfg;

};

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

+11 −18
Original line number Diff line number Diff line
@@ -369,11 +369,6 @@ static bool decide_dsc_target_bpp_x16( 
		/* enough bandwidth without dsc */

		*target_bpp_x16 = 0;

		should_use_dsc = false;

	} else if (policy->preferred_bpp_x16 > 0 &&

			policy->preferred_bpp_x16 <= range.max_target_bpp_x16 &&

			policy->preferred_bpp_x16 >= range.min_target_bpp_x16) {

		*target_bpp_x16 = policy->preferred_bpp_x16;

		should_use_dsc = true;

	} else if (target_bandwidth_kbps >= range.max_kbps) {

		/* use max target bpp allowed */

		*target_bpp_x16 = range.max_target_bpp_x16;
@@ -550,7 +545,7 @@ static bool setup_dsc_config( 
		int target_bandwidth_kbps,

		const struct dc_crtc_timing *timing,

		int min_slice_height_override,

		int max_dsc_target_bpp_limit_override_x16,

		int max_dsc_target_bpp_limit_override,

		struct dc_dsc_config *dsc_cfg)

{

	struct dsc_enc_caps dsc_common_caps;
@@ -569,7 +564,7 @@ static bool setup_dsc_config( 


	memset(dsc_cfg, 0, sizeof(struct dc_dsc_config));



	dc_dsc_get_policy_for_timing(timing, max_dsc_target_bpp_limit_override_x16, &policy);

	dc_dsc_get_policy_for_timing(timing, max_dsc_target_bpp_limit_override, &policy);

	pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;

	pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
@@ -870,8 +865,8 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, const uint8_t *dpcd_dsc_basic_da 
bool dc_dsc_compute_bandwidth_range(

		const struct display_stream_compressor *dsc,

		uint32_t dsc_min_slice_height_override,

		uint32_t min_bpp_x16,

		uint32_t max_bpp_x16,

		uint32_t min_bpp,

		uint32_t max_bpp,

		const struct dsc_dec_dpcd_caps *dsc_sink_caps,

		const struct dc_crtc_timing *timing,

		struct dc_dsc_bw_range *range)
@@ -888,10 +883,10 @@ bool dc_dsc_compute_bandwidth_range( 


	if (is_dsc_possible)

		is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing,

				dsc_min_slice_height_override, max_bpp_x16, &config);

				dsc_min_slice_height_override, max_bpp, &config);



	if (is_dsc_possible)

		get_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16, &dsc_common_caps, timing, range);

		get_dsc_bandwidth_range(min_bpp, max_bpp, &dsc_common_caps, timing, range);



	return is_dsc_possible;

}
@@ -900,7 +895,7 @@ bool dc_dsc_compute_config( 
		const struct display_stream_compressor *dsc,

		const struct dsc_dec_dpcd_caps *dsc_sink_caps,

		uint32_t dsc_min_slice_height_override,

		uint32_t max_target_bpp_limit_override_x16,

		uint32_t max_target_bpp_limit_override,

		uint32_t target_bandwidth_kbps,

		const struct dc_crtc_timing *timing,

		struct dc_dsc_config *dsc_cfg)
@@ -913,11 +908,11 @@ bool dc_dsc_compute_config( 
			&dsc_enc_caps,

			target_bandwidth_kbps,

			timing, dsc_min_slice_height_override,

			max_target_bpp_limit_override_x16, dsc_cfg);

			max_target_bpp_limit_override, dsc_cfg);

	return is_dsc_possible;

}



void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override_x16, struct dc_dsc_policy *policy)

void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override, struct dc_dsc_policy *policy)

{

	uint32_t bpc = 0;
@@ -972,15 +967,13 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t 
		return;

	}



	policy->preferred_bpp_x16 = timing->dsc_fixed_bits_per_pixel_x16;



	/* internal upper limit, default 16 bpp */

	if (policy->max_target_bpp > dsc_policy_max_target_bpp_limit)

		policy->max_target_bpp = dsc_policy_max_target_bpp_limit;



	/* apply override */

	if (max_target_bpp_limit_override_x16 && policy->max_target_bpp > max_target_bpp_limit_override_x16 / 16)

		policy->max_target_bpp = max_target_bpp_limit_override_x16 / 16;

	if (max_target_bpp_limit_override && policy->max_target_bpp > max_target_bpp_limit_override)

		policy->max_target_bpp = max_target_bpp_limit_override;



	/* enable DSC when not needed, default false */

	if (dsc_policy_enable_dsc_when_not_needed)