Commit b14d72ac authored by Fabrice Gasnier's avatar Fabrice Gasnier Committed by Jonathan Cameron
Browse files

counter: stm32-timer-cnt: fix ceiling miss-alignment with reload register 



Ceiling value may be miss-aligned with what's actually configured into the
ARR register. This is seen after probe as currently the ARR value is zero,
whereas ceiling value is set to the maximum. So:
- reading ceiling reports zero
- in case the counter gets enabled without any prior configuration,
  it won't count.
- in case the function gets set by the user 1st, (priv->ceiling) is used.

Fix it by getting rid of the cached "priv->ceiling" variable. Rather use
the ARR register value directly by using regmap read or write when needed.
There should be no drawback on performance as priv->ceiling isn't used in
performance critical path.
There's also no point in writing ARR while setting function (sms), so
it can be safely removed.

Fixes: ad29937e ("counter: Add STM32 Timer quadrature encoder")
Suggested-by: default avatarWilliam Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: default avatarFabrice Gasnier <fabrice.gasnier@foss.st.com>
Acked-by: default avatarWilliam Breathitt Gray <vilhelm.gray@gmail.com>
Cc: <Stable@vger.kernel.org>
Link: https://lore.kernel.org/r/1614793789-10346-1-git-send-email-fabrice.gasnier@foss.st.com


Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
parent e4c3e133

drivers/counter/stm32-timer-cnt.c

+3 −8
Original line number Diff line number Diff line
@@ -31,7 +31,6 @@ struct stm32_timer_cnt { 
	struct counter_device counter;

	struct regmap *regmap;

	struct clk *clk;

	u32 ceiling;

	u32 max_arr;

	bool enabled;

	struct stm32_timer_regs bak;
@@ -75,8 +74,10 @@ static int stm32_count_write(struct counter_device *counter, 
			     const unsigned long val)

{

	struct stm32_timer_cnt *const priv = counter->priv;

	u32 ceiling;



	if (val > priv->ceiling)

	regmap_read(priv->regmap, TIM_ARR, &ceiling);

	if (val > ceiling)

		return -EINVAL;



	return regmap_write(priv->regmap, TIM_CNT, val);
@@ -138,10 +139,6 @@ static int stm32_count_function_set(struct counter_device *counter, 


	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);



	/* TIMx_ARR register shouldn't be buffered (ARPE=0) */

	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);

	regmap_write(priv->regmap, TIM_ARR, priv->ceiling);



	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);



	/* Make sure that registers are updated */
@@ -199,7 +196,6 @@ static ssize_t stm32_count_ceiling_write(struct counter_device *counter, 
	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);

	regmap_write(priv->regmap, TIM_ARR, ceiling);



	priv->ceiling = ceiling;

	return len;

}
@@ -374,7 +370,6 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) 


	priv->regmap = ddata->regmap;

	priv->clk = ddata->clk;

	priv->ceiling = ddata->max_arr;

	priv->max_arr = ddata->max_arr;



	priv->counter.name = dev_name(dev);