Commit b14a3847 authored by Chengchang Tang's avatar Chengchang Tang Committed by Juan Zhou
Browse files

RDMA/hns: Fix missing capacities in query_device() 

driver inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I9FIHP



----------------------------------------------------------------------

This patch add max_ah and cq moderation capacities to
hns_roce_query_device().

Fixes: 9a443537 ("IB/hns: Add driver files for hns RoCE driver")
Signed-off-by: default avatarChengchang Tang <tangchengchang@huawei.com>
Signed-off-by: default avatarJuan Zhou <zhoujuan51@h-partners.com>
parent 813b1ee7

drivers/infiniband/hw/hns/hns_roce_device.h

+3 −0
Original line number Diff line number Diff line
@@ -103,6 +103,9 @@ 
#define CQ_BANKID_SHIFT 2

#define CQ_BANKID_MASK GENMASK(1, 0)



#define HNS_ROCE_MAX_CQ_COUNT 0xFFFF

#define HNS_ROCE_MAX_CQ_PERIOD 0xFFFF



enum {

	SERV_TYPE_RC,

	SERV_TYPE_UC,

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+1 −1
Original line number Diff line number Diff line
@@ -6166,7 +6166,7 @@ static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 
			dev_info(hr_dev->dev,

				 "cq_period(%u) reached the upper limit, adjusted to 65.\n",

				 cq_period);

			cq_period = HNS_ROCE_MAX_CQ_PERIOD;

			cq_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08;

		}

		cq_period *= HNS_ROCE_CLOCK_ADJUST;

	}

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+1 −1
Original line number Diff line number Diff line
@@ -1351,7 +1351,7 @@ struct fmea_ram_ecc { 


/* only for RNR timeout issue of HIP08 */

#define HNS_ROCE_CLOCK_ADJUST 1000

#define HNS_ROCE_MAX_CQ_PERIOD 65

#define HNS_ROCE_MAX_CQ_PERIOD_HIP08	65

#define HNS_ROCE_MAX_EQ_PERIOD 65

#define HNS_ROCE_RNR_TIMER_10NS 1

#define HNS_ROCE_1US_CFG 999

drivers/infiniband/hw/hns/hns_roce_main.c

+6 −0
Original line number Diff line number Diff line
@@ -250,6 +250,12 @@ static int hns_roce_query_device(struct ib_device *ib_dev, 
			    IB_ATOMIC_HCA : IB_ATOMIC_NONE;

	props->max_pkeys = 1;

	props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;

	props->max_ah = INT_MAX;

	props->cq_caps.max_cq_moderation_period = HNS_ROCE_MAX_CQ_PERIOD;

	props->cq_caps.max_cq_moderation_count = HNS_ROCE_MAX_CQ_COUNT;

	if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)

		props->cq_caps.max_cq_moderation_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08;



	if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {

		props->max_srq = hr_dev->caps.num_srqs;

		props->max_srq_wr = hr_dev->caps.max_srq_wrs;