Unverified Commit b1387062 authored by Srinivasa Rao Mandadapu's avatar Srinivasa Rao Mandadapu Committed by Mark Brown
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ASoC: qcom: Add regmap config support for codec dma driver 



Update regmap configuration for supporting headset playback and
capture and DMIC capture using codec dma interface

Signed-off-by: default avatarSrinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: default avatarVenkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: default avatarVenkata Prasad Potturu <quic_potturu@quicinc.com>
Reviewed-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/1645716828-15305-6-git-send-email-quic_srivasam@quicinc.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent dc8d9766

sound/soc/qcom/lpass-cpu.c

+252 −1
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ 
#define LPASS_CPU_I2S_SD2_3_MASK	GENMASK(3, 2)

#define LPASS_CPU_I2S_SD0_1_2_MASK	GENMASK(2, 0)

#define LPASS_CPU_I2S_SD0_1_2_3_MASK	GENMASK(3, 0)

#define LPASS_REG_READ 1

#define LPASS_REG_WRITE 0



/*

 * Channel maps for Quad channel playbacks on MI2S Secondary
@@ -798,6 +800,189 @@ static struct regmap_config lpass_hdmi_regmap_config = { 
	.cache_type = REGCACHE_FLAT,

};



static bool __lpass_rxtx_regmap_accessible(struct device *dev, unsigned int reg, bool rw)

{

	struct lpass_data *drvdata = dev_get_drvdata(dev);

	struct lpass_variant *v = drvdata->variant;

	int i;



	for (i = 0; i < v->rxtx_irq_ports; ++i) {

		if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))

			return true;

		if (reg == LPAIF_RXTX_IRQEN_REG(v, i))

			return true;

		if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))

			return true;

	}



	for (i = 0; i < v->rxtx_rdma_channels; ++i) {

		if (reg == LPAIF_CDC_RXTX_RDMACTL_REG(v, i, LPASS_CDC_DMA_RX0))

			return true;

		if (reg == LPAIF_CDC_RXTX_RDMABASE_REG(v, i, LPASS_CDC_DMA_RX0))

			return true;

		if (reg == LPAIF_CDC_RXTX_RDMABUFF_REG(v, i, LPASS_CDC_DMA_RX0))

			return true;

		if (rw == LPASS_REG_READ) {

			if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))

				return true;

		}

		if (reg == LPAIF_CDC_RXTX_RDMAPER_REG(v, i, LPASS_CDC_DMA_RX0))

			return true;

		if (reg == LPAIF_CDC_RXTX_RDMA_INTF_REG(v, i, LPASS_CDC_DMA_RX0))

			return true;

	}



	for (i = 0; i < v->rxtx_wrdma_channels; ++i) {

		if (reg == LPAIF_CDC_RXTX_WRDMACTL_REG(v, i + v->rxtx_wrdma_channel_start,

							LPASS_CDC_DMA_TX3))

			return true;

		if (reg == LPAIF_CDC_RXTX_WRDMABASE_REG(v, i + v->rxtx_wrdma_channel_start,

							LPASS_CDC_DMA_TX3))

			return true;

		if (reg == LPAIF_CDC_RXTX_WRDMABUFF_REG(v, i + v->rxtx_wrdma_channel_start,

							LPASS_CDC_DMA_TX3))

			return true;

		if (rw == LPASS_REG_READ) {

			if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))

				return true;

		}

		if (reg == LPAIF_CDC_RXTX_WRDMAPER_REG(v, i + v->rxtx_wrdma_channel_start,

							LPASS_CDC_DMA_TX3))

			return true;

		if (reg == LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, i + v->rxtx_wrdma_channel_start,

							LPASS_CDC_DMA_TX3))

			return true;

	}

	return false;

}



static bool lpass_rxtx_regmap_writeable(struct device *dev, unsigned int reg)

{

	return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_WRITE);

}



static bool lpass_rxtx_regmap_readable(struct device *dev, unsigned int reg)

{

	return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_READ);

}



static bool lpass_rxtx_regmap_volatile(struct device *dev, unsigned int reg)

{

	struct lpass_data *drvdata = dev_get_drvdata(dev);

	struct lpass_variant *v = drvdata->variant;

	int i;



	for (i = 0; i < v->rxtx_irq_ports; ++i) {

		if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))

			return true;

		if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))

			return true;

	}



	for (i = 0; i < v->rxtx_rdma_channels; ++i)

		if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))

			return true;



	for (i = 0; i < v->rxtx_wrdma_channels; ++i)

		if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i + v->rxtx_wrdma_channel_start,

							LPASS_CDC_DMA_TX3))

			return true;



	return false;

}



static bool __lpass_va_regmap_accessible(struct device *dev, unsigned int reg, bool rw)

{

	struct lpass_data *drvdata = dev_get_drvdata(dev);

	struct lpass_variant *v = drvdata->variant;

	int i;



	for (i = 0; i < v->va_irq_ports; ++i) {

		if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))

			return true;

		if (reg == LPAIF_VA_IRQEN_REG(v, i))

			return true;

		if (reg == LPAIF_VA_IRQSTAT_REG(v, i))

			return true;

	}



	for (i = 0; i < v->va_wrdma_channels; ++i) {

		if (reg == LPAIF_CDC_VA_WRDMACTL_REG(v, i + v->va_wrdma_channel_start,

							LPASS_CDC_DMA_VA_TX0))

			return true;

		if (reg == LPAIF_CDC_VA_WRDMABASE_REG(v, i + v->va_wrdma_channel_start,

							LPASS_CDC_DMA_VA_TX0))

			return true;

		if (reg == LPAIF_CDC_VA_WRDMABUFF_REG(v, i + v->va_wrdma_channel_start,

							LPASS_CDC_DMA_VA_TX0))

			return true;

		if (rw == LPASS_REG_READ) {

			if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,

							LPASS_CDC_DMA_VA_TX0))

				return true;

		}

		if (reg == LPAIF_CDC_VA_WRDMAPER_REG(v, i + v->va_wrdma_channel_start,

							LPASS_CDC_DMA_VA_TX0))

			return true;

		if (reg == LPAIF_CDC_VA_WRDMA_INTF_REG(v, i + v->va_wrdma_channel_start,

							LPASS_CDC_DMA_VA_TX0))

			return true;

	}

	return false;

}



static bool lpass_va_regmap_writeable(struct device *dev, unsigned int reg)

{

	return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_WRITE);

}



static bool lpass_va_regmap_readable(struct device *dev, unsigned int reg)

{

	return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_READ);

}



static bool lpass_va_regmap_volatile(struct device *dev, unsigned int reg)

{

	struct lpass_data *drvdata = dev_get_drvdata(dev);

	struct lpass_variant *v = drvdata->variant;

	int i;



	for (i = 0; i < v->va_irq_ports; ++i) {

		if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))

			return true;

		if (reg == LPAIF_VA_IRQSTAT_REG(v, i))

			return true;

	}



	for (i = 0; i < v->va_wrdma_channels; ++i) {

		if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,

							LPASS_CDC_DMA_VA_TX0))

			return true;

	}



	return false;

}



static struct regmap_config lpass_rxtx_regmap_config = {

	.reg_bits = 32,

	.reg_stride = 4,

	.val_bits = 32,

	.writeable_reg = lpass_rxtx_regmap_writeable,

	.readable_reg = lpass_rxtx_regmap_readable,

	.volatile_reg = lpass_rxtx_regmap_volatile,

	.cache_type = REGCACHE_FLAT,

};



static struct regmap_config lpass_va_regmap_config = {

	.reg_bits = 32,

	.reg_stride = 4,

	.val_bits = 32,

	.writeable_reg = lpass_va_regmap_writeable,

	.readable_reg = lpass_va_regmap_readable,

	.volatile_reg = lpass_va_regmap_volatile,

	.cache_type = REGCACHE_FLAT,

};



static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev,

						struct device_node *node,

						const char *name)
@@ -857,6 +1042,8 @@ static void of_lpass_cpu_parse_dai_data(struct device *dev, 
		}

		if (id == LPASS_DP_RX) {

			data->hdmi_port_enable = 1;

		} else if (is_cdc_dma_port(id)) {

			data->codec_dma_enable = 1;

		} else {

			data->mi2s_playback_sd_mode[id] =

				of_lpass_cpu_parse_sd_lines(dev, node,
@@ -868,10 +1055,33 @@ static void of_lpass_cpu_parse_dai_data(struct device *dev, 
	}

}



static int of_lpass_cdc_dma_clks_parse(struct device *dev,

					struct lpass_data *data)

{

	data->codec_mem0 = devm_clk_get(dev, "audio_cc_codec_mem0");

	if (IS_ERR(data->codec_mem0))

		return PTR_ERR(data->codec_mem0);



	data->codec_mem1 = devm_clk_get(dev, "audio_cc_codec_mem1");

	if (IS_ERR(data->codec_mem1))

		return PTR_ERR(data->codec_mem1);



	data->codec_mem2 = devm_clk_get(dev, "audio_cc_codec_mem2");

	if (IS_ERR(data->codec_mem2))

		return PTR_ERR(data->codec_mem2);



	data->va_mem0 = devm_clk_get(dev, "aon_cc_va_mem0");

	if (IS_ERR(data->va_mem0))

		return PTR_ERR(data->va_mem0);



	return 0;

}



int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)

{

	struct lpass_data *drvdata;

	struct device_node *dsp_of_node;

	struct resource *res;

	struct lpass_variant *variant;

	struct device *dev = &pdev->dev;

	const struct of_device_id *match;
@@ -897,6 +1107,47 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) 


	of_lpass_cpu_parse_dai_data(dev, drvdata);



	if (drvdata->codec_dma_enable) {

		drvdata->rxtx_lpaif =

				devm_platform_ioremap_resource_byname(pdev, "lpass-rxtx-lpaif");

		if (IS_ERR(drvdata->rxtx_lpaif))

			return PTR_ERR(drvdata->rxtx_lpaif);



		drvdata->va_lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-va-lpaif");

		if (IS_ERR(drvdata->va_lpaif))

			return PTR_ERR(drvdata->va_lpaif);



		lpass_rxtx_regmap_config.max_register = LPAIF_CDC_RXTX_WRDMAPER_REG(variant,

					variant->rxtx_wrdma_channels +

					variant->rxtx_wrdma_channel_start, LPASS_CDC_DMA_TX3);



		drvdata->rxtx_lpaif_map = devm_regmap_init_mmio(dev, drvdata->rxtx_lpaif,

					&lpass_rxtx_regmap_config);

		if (IS_ERR(drvdata->rxtx_lpaif_map))

			return PTR_ERR(drvdata->rxtx_lpaif_map);



		lpass_va_regmap_config.max_register = LPAIF_CDC_VA_WRDMAPER_REG(variant,

					variant->va_wrdma_channels +

					variant->va_wrdma_channel_start, LPASS_CDC_DMA_VA_TX0);



		drvdata->va_lpaif_map = devm_regmap_init_mmio(dev, drvdata->va_lpaif,

					&lpass_va_regmap_config);

		if (IS_ERR(drvdata->va_lpaif_map))

			return PTR_ERR(drvdata->va_lpaif_map);



		ret = of_lpass_cdc_dma_clks_parse(dev, drvdata);

		if (ret) {

			dev_err(dev, "failed to get cdc dma clocks %d\n", ret);

			return ret;

		}



		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-rxtx-cdc-dma-lpm");

		drvdata->rxtx_cdc_dma_lpm_buf = res->start;



		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-va-cdc-dma-lpm");

		drvdata->va_cdc_dma_lpm_buf = res->start;

	}



	drvdata->lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-lpaif");

	if (IS_ERR(drvdata->lpaif))

		return PTR_ERR(drvdata->lpaif);
@@ -939,7 +1190,7 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) 


	for (i = 0; i < variant->num_dai; i++) {

		dai_id = variant->dai_driver[i].id;

		if (dai_id == LPASS_DP_RX)

		if (dai_id == LPASS_DP_RX || is_cdc_dma_port(dai_id))

			continue;



		drvdata->mi2s_osr_clk[dai_id] = devm_clk_get_optional(dev,