Commit b12deb5e authored by Leon Yen's avatar Leon Yen Committed by Felix Fietkau
Browse files

mt76: mt7921s: fix mt7921s_mcu_[fw|drv]_pmctrl



According to the firmware behavior (even the oldest one in linux-firmware)
If the firmware is downloaded, MT7921S must rely on the additional mailbox
mechanism that resides in firmware to check if the device is the right
state for mt7921s_mcu_[fw|drv]_pmctrl. Otherwise, we still apply the old
way for that.

That is a necessary patch before we enable runtime pm for mt7921s as
default.

Fixes: 48fab5bb ("mt76: mt7921: introduce mt7921s support")
Co-developed-by: default avatarSean Wang <sean.wang@mediatek.com>
Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Signed-off-by: default avatarLeon Yen <leon.yen@mediatek.com>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent b1fe07ed
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+38 −0
Original line number Diff line number Diff line
@@ -49,6 +49,26 @@ mt7921s_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
	return ret;
}

static u32 mt7921s_read_rm3r(struct mt7921_dev *dev)
{
	struct mt76_sdio *sdio = &dev->mt76.sdio;

	return sdio_readl(sdio->func, MCR_D2HRM3R, NULL);
}

static u32 mt7921s_clear_rm3r_drv_own(struct mt7921_dev *dev)
{
	struct mt76_sdio *sdio = &dev->mt76.sdio;
	u32 val;

	val = sdio_readl(sdio->func, MCR_D2HRM3R, NULL);
	if (val)
		sdio_writel(sdio->func, H2D_SW_INT_CLEAR_MAILBOX_ACK,
			    MCR_WSICR, NULL);

	return val;
}

int mt7921s_mcu_init(struct mt7921_dev *dev)
{
	static const struct mt76_mcu_ops mt7921s_mcu_ops = {
@@ -88,6 +108,12 @@ int mt7921s_mcu_drv_pmctrl(struct mt7921_dev *dev)

	err = readx_poll_timeout(mt76s_read_pcr, &dev->mt76, status,
				 status & WHLPCR_IS_DRIVER_OWN, 2000, 1000000);

	if (!err && test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state))
		err = readx_poll_timeout(mt7921s_read_rm3r, dev, status,
					 status & D2HRM3R_IS_DRIVER_OWN,
					 2000, 1000000);

	sdio_release_host(func);

	if (err < 0) {
@@ -115,12 +141,24 @@ int mt7921s_mcu_fw_pmctrl(struct mt7921_dev *dev)

	sdio_claim_host(func);

	if (test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state)) {
		err = readx_poll_timeout(mt7921s_clear_rm3r_drv_own,
					 dev, status,
					 !(status & D2HRM3R_IS_DRIVER_OWN),
					 2000, 1000000);
		if (err < 0) {
			dev_err(dev->mt76.dev, "mailbox ACK not cleared\n");
			goto err;
		}
	}

	sdio_writel(func, WHLPCR_FW_OWN_REQ_SET, MCR_WHLPCR, NULL);

	err = readx_poll_timeout(mt76s_read_pcr, &dev->mt76, status,
				 !(status & WHLPCR_IS_DRIVER_OWN), 2000, 1000000);
	sdio_release_host(func);

err:
	if (err < 0) {
		dev_err(dev->mt76.dev, "firmware own failed\n");
		clear_bit(MT76_STATE_PM, &mphy->state);
+2 −0
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@
#define MCR_H2DSM0R			0x0070
#define H2D_SW_INT_READ			BIT(16)
#define H2D_SW_INT_WRITE		BIT(17)
#define H2D_SW_INT_CLEAR_MAILBOX_ACK	BIT(22)

#define MCR_H2DSM1R			0x0074
#define MCR_D2HRM0R			0x0078
@@ -109,6 +110,7 @@
#define MCR_H2DSM2R			0x0160 /* supported in CONNAC2 */
#define MCR_H2DSM3R			0x0164 /* supported in CONNAC2 */
#define MCR_D2HRM3R			0x0174 /* supported in CONNAC2 */
#define D2HRM3R_IS_DRIVER_OWN		BIT(0)
#define MCR_WTQCR8			0x0190 /* supported in CONNAC2 */
#define MCR_WTQCR9			0x0194 /* supported in CONNAC2 */
#define MCR_WTQCR10			0x0198 /* supported in CONNAC2 */