Commit b0eed085 authored by Longfang Liu's avatar Longfang Liu Committed by Alex Williamson
Browse files

hisi_acc_vfio_pci: Add support for VFIO live migration 



VMs assigned with HiSilicon ACC VF devices can now perform live migration
if the VF devices are bind to the hisi_acc_vfio_pci driver.

Just like ACC PF/VF drivers this VFIO driver also make use of the HiSilicon
QM interface. QM stands for Queue Management which is a generic IP used by
ACC devices. It provides a generic PCIe interface for the CPU and the ACC
devices to share a group of queues.

QM integrated into an accelerator provides queue management service.
Queues can be assigned to PF and VFs, and queues can be controlled by
unified mailboxes and doorbells.

The QM driver (drivers/crypto/hisilicon/qm.c) provides generic
interfaces to ACC drivers to manage the QM.

Signed-off-by: default avatarLongfang Liu <liulongfang@huawei.com>
Reviewed-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Signed-off-by: default avatarShameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Link: https://lore.kernel.org/r/20220308184902.2242-9-shameerali.kolothum.thodi@huawei.com
Reviewed-by: default avatarKevin Tian <kevin.tian@intel.com>
Signed-off-by: default avatarAlex Williamson <alex.williamson@redhat.com>
parent 1e459b25

drivers/vfio/pci/hisilicon/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -3,6 +3,11 @@ config HISI_ACC_VFIO_PCI 
	tristate "VFIO PCI support for HiSilicon ACC devices"

	depends on ARM64 || (COMPILE_TEST && 64BIT)

	depends on VFIO_PCI_CORE

	depends on PCI_MSI

	depends on CRYPTO_DEV_HISI_QM

	depends on CRYPTO_DEV_HISI_HPRE

	depends on CRYPTO_DEV_HISI_SEC2

	depends on CRYPTO_DEV_HISI_ZIP

	help

	  This provides generic PCI support for HiSilicon ACC devices

	  using the VFIO framework.

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

+1067 −18

File changed.

Preview size limit exceeded, changes collapsed.

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h

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+114 −0
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/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (c) 2021 HiSilicon Ltd. */



#ifndef HISI_ACC_VFIO_PCI_H

#define HISI_ACC_VFIO_PCI_H



#include <linux/hisi_acc_qm.h>



#define MB_POLL_PERIOD_US		10

#define MB_POLL_TIMEOUT_US		1000

#define QM_CACHE_WB_START		0x204

#define QM_CACHE_WB_DONE		0x208

#define QM_MB_CMD_PAUSE_QM		0xe

#define QM_ABNORMAL_INT_STATUS		0x100008

#define QM_IFC_INT_STATUS		0x0028

#define SEC_CORE_INT_STATUS		0x301008

#define HPRE_HAC_INT_STATUS		0x301800

#define HZIP_CORE_INT_STATUS		0x3010AC

#define QM_QUE_ISO_CFG			0x301154



#define QM_VFT_CFG_RDY			0x10006c

#define QM_VFT_CFG_OP_WR		0x100058

#define QM_VFT_CFG_TYPE			0x10005c

#define QM_VFT_CFG			0x100060

#define QM_VFT_CFG_OP_ENABLE		0x100054

#define QM_VFT_CFG_DATA_L		0x100064

#define QM_VFT_CFG_DATA_H		0x100068



#define ERROR_CHECK_TIMEOUT		100

#define CHECK_DELAY_TIME		100



#define QM_SQC_VFT_BASE_SHIFT_V2	28

#define QM_SQC_VFT_BASE_MASK_V2		GENMASK(15, 0)

#define QM_SQC_VFT_NUM_SHIFT_V2		45

#define QM_SQC_VFT_NUM_MASK_V2		GENMASK(9, 0)



/* RW regs */

#define QM_REGS_MAX_LEN		7

#define QM_REG_ADDR_OFFSET	0x0004



#define QM_XQC_ADDR_OFFSET	32U

#define QM_VF_AEQ_INT_MASK	0x0004

#define QM_VF_EQ_INT_MASK	0x000c

#define QM_IFC_INT_SOURCE_V	0x0020

#define QM_IFC_INT_MASK		0x0024

#define QM_IFC_INT_SET_V	0x002c

#define QM_QUE_ISO_CFG_V	0x0030

#define QM_PAGE_SIZE		0x0034



#define QM_EQC_DW0		0X8000

#define QM_AEQC_DW0		0X8020



struct acc_vf_data {

#define QM_MATCH_SIZE offsetofend(struct acc_vf_data, qm_rsv_state)

	/* QM match information */

#define ACC_DEV_MAGIC	0XCDCDCDCDFEEDAACC

	u64 acc_magic;

	u32 qp_num;

	u32 dev_id;

	u32 que_iso_cfg;

	u32 qp_base;

	u32 vf_qm_state;

	/* QM reserved match information */

	u32 qm_rsv_state[3];



	/* QM RW regs */

	u32 aeq_int_mask;

	u32 eq_int_mask;

	u32 ifc_int_source;

	u32 ifc_int_mask;

	u32 ifc_int_set;

	u32 page_size;



	/* QM_EQC_DW has 7 regs */

	u32 qm_eqc_dw[7];



	/* QM_AEQC_DW has 7 regs */

	u32 qm_aeqc_dw[7];



	/* QM reserved 5 regs */

	u32 qm_rsv_regs[5];

	u32 padding;

	/* qm memory init information */

	u64 eqe_dma;

	u64 aeqe_dma;

	u64 sqc_dma;

	u64 cqc_dma;

};



struct hisi_acc_vf_migration_file {

	struct file *filp;

	struct mutex lock;

	bool disabled;



	struct acc_vf_data vf_data;

	size_t total_length;

};



struct hisi_acc_vf_core_device {

	struct vfio_pci_core_device core_device;

	/* for migration state */

	struct mutex state_mutex;

	enum vfio_device_mig_state mig_state;

	struct pci_dev *pf_dev;

	struct pci_dev *vf_dev;

	struct hisi_qm *pf_qm;

	struct hisi_qm vf_qm;

	u32 vf_qm_state;

	int vf_id;



	struct hisi_acc_vf_migration_file *resuming_migf;

	struct hisi_acc_vf_migration_file *saving_migf;

};

#endif /* HISI_ACC_VFIO_PCI_H */