Commit b0c1a994 authored by Thierry Reding's avatar Thierry Reding
Browse files

arm64: tegra: Fixup iommu-map property formatting 



Make sure that each phandle-array is enclosed in a set of angular
brackets and properly indent each entry.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent a1e3de6e

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+8 −9
Original line number Diff line number Diff line
@@ -1485,15 +1485,14 @@ 
		iommus = <&smmu TEGRA186_SID_HOST1X>;



		/* Context isolation domains */

		iommu-map = <

			0 &smmu TEGRA186_SID_HOST1X_CTX0 1

			1 &smmu TEGRA186_SID_HOST1X_CTX1 1

			2 &smmu TEGRA186_SID_HOST1X_CTX2 1

			3 &smmu TEGRA186_SID_HOST1X_CTX3 1

			4 &smmu TEGRA186_SID_HOST1X_CTX4 1

			5 &smmu TEGRA186_SID_HOST1X_CTX5 1

			6 &smmu TEGRA186_SID_HOST1X_CTX6 1

			7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;

		iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,

			    <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>,

			    <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>,

			    <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>,

			    <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>,

			    <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>,

			    <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>,

			    <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;



		dpaux1: dpaux@15040000 {

			compatible = "nvidia,tegra186-dpaux";

arch/arm64/boot/dts/nvidia/tegra194.dtsi

+8 −9
Original line number Diff line number Diff line
@@ -1869,15 +1869,14 @@ 
			iommus = <&smmu TEGRA194_SID_HOST1X>;



			/* Context isolation domains */

			iommu-map = <

				0 &smmu TEGRA194_SID_HOST1X_CTX0 1

				1 &smmu TEGRA194_SID_HOST1X_CTX1 1

				2 &smmu TEGRA194_SID_HOST1X_CTX2 1

				3 &smmu TEGRA194_SID_HOST1X_CTX3 1

				4 &smmu TEGRA194_SID_HOST1X_CTX4 1

				5 &smmu TEGRA194_SID_HOST1X_CTX5 1

				6 &smmu TEGRA194_SID_HOST1X_CTX6 1

				7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;

			iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,

				    <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>,

				    <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>,

				    <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>,

				    <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>,

				    <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>,

				    <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>,

				    <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;



			nvdec@15140000 {

				compatible = "nvidia,tegra194-nvdec";