Commit b0b46118 authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo
Browse files

arm64: dts: imx8qm: add cache info 



i.MX8QM A53 Cluster has 32KB Icache, 32KB Dcache and 1MB L2 Cache
  - Icache is 2-way set associative
  - Dcache is 4-way set associative
  - L2cache is 16-way set associative
  - Line size are 64bytes

A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache
 - ICache is 3-way set-associative
 - Dcache is 2-way set-associative
 - L2Cache is 16-way set-associative
 - Line size are 64bytes

Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent cb551b5e

arch/arm64/boot/dts/freescale/imx8qm.dtsi

+38 −0
Original line number Diff line number Diff line
@@ -57,6 +57,12 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

		};
@@ -65,6 +71,12 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x1>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

		};
@@ -73,6 +85,12 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x2>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

		};
@@ -81,6 +99,12 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x3>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

		};
@@ -89,6 +113,12 @@ 
			compatible = "arm,cortex-a72", "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			i-cache-size = <0xC000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&A72_L2>;

		};
@@ -102,10 +132,18 @@ 


		A53_L2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-size = <0x100000>;

			cache-line-size = <64>;

			cache-sets = <1024>;

		};



		A72_L2: l2-cache1 {

			compatible = "cache";

			cache-level = <2>;

			cache-size = <0x100000>;

			cache-line-size = <64>;

			cache-sets = <1024>;

		};

	};