Commit b04cb192 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Add DCN3.1 DMCUB 



DMCU-B (Display Micro-Controller Unit B) is a display microcontroller
used for shared display functionality with BIOS and for advanced
power saving display features.

Extends the command header to include new DCN3.1 functionality.

Adds new interfaces to DC dmub interface as well for z-state support.

Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 56546ffc

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

+23 −0
Original line number Diff line number Diff line
@@ -180,6 +180,29 @@ bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 
		       dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,

		       stream_mask, timeout) == DMUB_STATUS_OK;

}

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)

{

	struct dmub_srv *dmub;

	struct dc_context *dc_ctx;

	union dmub_fw_boot_status boot_status;

	enum dmub_status status;



	if (!dc_dmub_srv || !dc_dmub_srv->dmub)

		return false;



	dmub = dc_dmub_srv->dmub;

	dc_ctx = dc_dmub_srv->ctx;



	status = dmub_srv_get_fw_boot_status(dmub, &boot_status);

	if (status != DMUB_STATUS_OK) {

		DC_ERROR("Error querying DMUB boot status: error=%d\n", status);

		return false;

	}



	return boot_status.bits.restore_required;

}

#endif



bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)

{

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

+3 −0
Original line number Diff line number Diff line
@@ -62,6 +62,9 @@ bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub 
bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,

				    unsigned int stream_mask);



#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv);

#endif

bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry);



void dc_dmub_trace_event_control(struct dc *dc, bool enable);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

+12 −0
Original line number Diff line number Diff line
@@ -73,6 +73,9 @@ extern "C" { 
/* Forward declarations */

struct dmub_srv;

struct dmub_srv_common_regs;

#ifdef CONFIG_DRM_AMD_DC_DCN3_1

struct dmub_srv_dcn31_regs;

#endif



struct dmcub_trace_buf_entry;
@@ -94,6 +97,9 @@ enum dmub_asic { 
	DMUB_ASIC_DCN301,

	DMUB_ASIC_DCN302,

	DMUB_ASIC_DCN303,

#ifdef CONFIG_DRM_AMD_DC_DCN3_1

	DMUB_ASIC_DCN31,

#endif

	DMUB_ASIC_MAX,

};
@@ -232,6 +238,9 @@ struct dmub_srv_hw_params { 
	uint32_t psp_version;

	bool load_inst_const;

	bool skip_panel_power_sequence;

#ifdef CONFIG_DRM_AMD_DC_DCN3_1

	bool disable_z10;

#endif

};



/**
@@ -364,6 +373,9 @@ struct dmub_srv { 


	/* private: internal use only */

	const struct dmub_srv_common_regs *regs;

#ifdef CONFIG_DRM_AMD_DC_DCN3_1

	const struct dmub_srv_dcn31_regs *regs_dcn31;

#endif



	struct dmub_srv_base_funcs funcs;

	struct dmub_srv_hw_funcs hw_funcs;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

+118 −0
Original line number Diff line number Diff line
@@ -337,7 +337,11 @@ union dmub_fw_boot_options { 
		uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */

		uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */

		uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */

#ifdef CONFIG_DRM_AMD_DC_DCN3_1

		uint32_t z10_disable: 1; /**< 1 to disable z10 */

#else

		uint32_t reserved_unreleased: 1; /**< reserved for an unreleased feature */

#endif

		uint32_t reserved : 25; /**< reserved */

	} bits; /**< boot bits */

	uint32_t all; /**< 32-bit access to bits */
@@ -602,6 +606,20 @@ enum dmub_cmd_type { 
	 * Command type used for OUTBOX1 notification enable

	 */

	DMUB_CMD__OUTBOX1_ENABLE = 71,

#ifdef CONFIG_DRM_AMD_DC_DCN3_1

	/**

	 * Command type used for all idle optimization commands.

	 */

	DMUB_CMD__IDLE_OPT = 72,

	/**

	 * Command type used for all clock manager commands.

	 */

	DMUB_CMD__CLK_MGR = 73,

	/**

	 * Command type used for all panel control commands.

	 */

	DMUB_CMD__PANEL_CNTL = 74,

#endif

	/**

	 * Command type used for all VBIOS interface commands.

	 */
@@ -811,6 +829,53 @@ struct dmub_rb_cmd_mall { 
	uint8_t reserved2; /**< Reserved bits */

};



#ifdef CONFIG_DRM_AMD_DC_DCN3_1



/**

 * enum dmub_cmd_idle_opt_type - Idle optimization command type.

 */

enum dmub_cmd_idle_opt_type {

	/**

	 * DCN hardware restore.

	 */

	DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,

};



/**

 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.

 */

struct dmub_rb_cmd_idle_opt_dcn_restore {

	struct dmub_cmd_header header; /**< header */

};



/**

 * struct dmub_clocks - Clock update notification.

 */

struct dmub_clocks {

	uint32_t dispclk_khz; /**< dispclk kHz */

	uint32_t dppclk_khz; /**< dppclk kHz */

	uint32_t dcfclk_khz; /**< dcfclk kHz */

	uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */

};



/**

 * enum dmub_cmd_clk_mgr_type - Clock manager commands.

 */

enum dmub_cmd_clk_mgr_type {

	/**

	 * Notify DMCUB of clock update.

	 */

	DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,

};



/**

 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.

 */

struct dmub_rb_cmd_clk_mgr_notify_clocks {

	struct dmub_cmd_header header; /**< header */

	struct dmub_clocks clocks; /**< clock data */

};

#endif

/**

 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.

 */
@@ -1956,6 +2021,43 @@ struct dmub_rb_cmd_drr_update { 
		struct dmub_optc_state dmub_optc_state_req;

};



#ifdef CONFIG_DRM_AMD_DC_DCN3_1

/**

 * enum dmub_cmd_panel_cntl_type - Panel control command.

 */

enum dmub_cmd_panel_cntl_type {

	/**

	 * Initializes embedded panel hardware blocks.

	 */

	DMUB_CMD__PANEL_CNTL_HW_INIT = 0,

	/**

	 * Queries backlight info for the embedded panel.

	 */

	DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,

};



/**

 * struct dmub_cmd_panel_cntl_data - Panel control data.

 */

struct dmub_cmd_panel_cntl_data {

	uint32_t inst; /**< panel instance */

	uint32_t current_backlight; /* in/out */

	uint32_t bl_pwm_cntl; /* in/out */

	uint32_t bl_pwm_period_cntl; /* in/out */

	uint32_t bl_pwm_ref_div1; /* in/out */

	uint8_t is_backlight_on : 1; /* in/out */

	uint8_t is_powered_on : 1; /* in/out */

};



/**

 * struct dmub_rb_cmd_panel_cntl - Panel control command.

 */

struct dmub_rb_cmd_panel_cntl {

	struct dmub_cmd_header header; /**< header */

	struct dmub_cmd_panel_cntl_data data; /**< payload */

};

#endif



/**

 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.

 */
@@ -2053,6 +2155,22 @@ union dmub_rb_cmd { 
	 * Definition of a DMUB_CMD__MALL command.

	 */

	struct dmub_rb_cmd_mall mall;

#ifdef CONFIG_DRM_AMD_DC_DCN3_1

	/**

	 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.

	 */

	struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;



	/**

	 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.

	 */

	struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;



	/**

	 * Definition of DMUB_CMD__PANEL_CNTL commands.

	 */

	struct dmub_rb_cmd_panel_cntl panel_cntl;

#endif

	/**

	 * Definition of a DMUB_CMD__ABM_SET_PIPE command.

	 */

drivers/gpu/drm/amd/display/dmub/src/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -24,6 +24,9 @@ DMUB = dmub_srv.o dmub_srv_stat.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o 
DMUB += dmub_dcn30.o dmub_dcn301.o

DMUB += dmub_dcn302.o

DMUB += dmub_dcn303.o

ifdef CONFIG_DRM_AMD_DC_DCN3_1

DMUB += dmub_dcn31.o

endif



AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))