Commit affac98a authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Helgaas
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PCI: qcom: Remove unnecessary pipe_clk handling 

PCIe PHY drivers (both QMP and PCIe2) already do clk_prepare_enable() /
clk_prepare_disable() pipe_clk. Remove extra calls to enable/disable
this clock from the PCIe driver, so that the PHY driver can manage the
clock on its own.

[bhelgaas: rebase on Robert Marko's DBI cleanup:
https://lore.kernel.org/r/20220623155004.688090-2-robimarko@gmail.com]
Link: https://lore.kernel.org/r/20220608105238.2973600-5-dmitry.baryshkov@linaro.org


Tested-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Reviewed-by: default avatarStephen Boyd <sboyd@kernel.org>
Acked-by: default avatarStanimir Varbanov <svarbanov@mm-sol.com>
parent 36d9018d

drivers/pci/controller/dwc/pcie-qcom.c

+3 −34
Original line number Diff line number Diff line
@@ -128,7 +128,6 @@ struct qcom_pcie_resources_2_3_2 { 
	struct clk *master_clk;

	struct clk *slave_clk;

	struct clk *cfg_clk;

	struct clk *pipe_clk;

	struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];

};
@@ -165,7 +164,6 @@ struct qcom_pcie_resources_2_7_0 { 
	int num_clks;

	struct regulator_bulk_data supplies[2];

	struct reset_control *pci_reset;

	struct clk *pipe_clk;

	struct clk *pipe_clk_src;

	struct clk *phy_pipe_clk;

	struct clk *ref_clk_src;
@@ -608,8 +606,7 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) 
	if (IS_ERR(res->slave_clk))

		return PTR_ERR(res->slave_clk);



	res->pipe_clk = devm_clk_get(dev, "pipe");

	return PTR_ERR_OR_ZERO(res->pipe_clk);

	return 0;

}



static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
@@ -624,13 +621,6 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) 
	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);

}



static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;



	clk_disable_unprepare(res->pipe_clk);

}



static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
@@ -685,11 +675,7 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) 


static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;

	u32 val;

	int ret;



	/* enable PCIe clocks and resets */

	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
@@ -712,12 +698,6 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) 
	val |= BIT(31);

	writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);



	ret = clk_prepare_enable(res->pipe_clk);

	if (ret) {

		dev_err(dev, "cannot prepare/enable pipe clock\n");

		return ret;

	}



	return 0;

}
@@ -1222,8 +1202,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) 
			return PTR_ERR(res->ref_clk_src);

	}



	res->pipe_clk = devm_clk_get(dev, "pipe");

	return PTR_ERR_OR_ZERO(res->pipe_clk);

	return 0;

}



static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
@@ -1316,14 +1295,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) 
	if (pcie->cfg->pipe_clk_need_muxing)

		clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk);



	return clk_prepare_enable(res->pipe_clk);

}



static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;



	clk_disable_unprepare(res->pipe_clk);

	return 0;

}



static int qcom_pcie_link_up(struct dw_pcie *pci)
@@ -1477,7 +1449,6 @@ static const struct qcom_pcie_ops ops_2_3_2 = { 
	.init = qcom_pcie_init_2_3_2,

	.post_init = qcom_pcie_post_init_2_3_2,

	.deinit = qcom_pcie_deinit_2_3_2,

	.post_deinit = qcom_pcie_post_deinit_2_3_2,

	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,

};
@@ -1506,7 +1477,6 @@ static const struct qcom_pcie_ops ops_2_7_0 = { 
	.deinit = qcom_pcie_deinit_2_7_0,

	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,

	.post_init = qcom_pcie_post_init_2_7_0,

	.post_deinit = qcom_pcie_post_deinit_2_7_0,

};



/* Qcom IP rev.: 1.9.0 */
@@ -1516,7 +1486,6 @@ static const struct qcom_pcie_ops ops_1_9_0 = { 
	.deinit = qcom_pcie_deinit_2_7_0,

	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,

	.post_init = qcom_pcie_post_init_2_7_0,

	.post_deinit = qcom_pcie_post_deinit_2_7_0,

	.config_sid = qcom_pcie_config_sid_sm8250,

};