Unverified Commit afc7a583 authored by Zong Li's avatar Zong Li Committed by Palmer Dabbelt
Browse files

soc: sifive: ccache: define the macro for the register shifts 



Define the macro for the register shifts, it could make the code be
more readable

Signed-off-by: default avatarZong Li <zong.li@sifive.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220913061817.22564-7-zong.li@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 696ab9bd

drivers/soc/sifive/sifive_ccache.c

+11 −5
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <linux/of_irq.h>

#include <linux/of_address.h>

#include <linux/device.h>

#include <linux/bitfield.h>

#include <asm/cacheinfo.h>

#include <soc/sifive/sifive_ccache.h>
@@ -33,6 +34,11 @@ 
#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168



#define SIFIVE_CCACHE_CONFIG 0x00

#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0)

#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8)

#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)

#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)



#define SIFIVE_CCACHE_WAYENABLE 0x08

#define SIFIVE_CCACHE_ECCINJECTERR 0x40
@@ -87,11 +93,11 @@ static void ccache_config_read(void) 
	u32 cfg;



	cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);



	pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",

		(cfg & 0xff), (cfg >> 8) & 0xff,

		BIT_ULL((cfg >> 16) & 0xff),

		BIT_ULL((cfg >> 24) & 0xff));

	pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n",

		FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg),

		FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg),

		BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)),

		BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg)));



	cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);

	pr_info("Index of the largest way enabled: %u\n", cfg);