Commit afbef301 authored by Kan Liang's avatar Kan Liang Committed by Ingo Molnar
Browse files

perf/x86/intel: Set PERF_ATTACH_SCHED_CB for large PEBS and LBR 



To supply a PID/TID for large PEBS, it requires flushing the PEBS buffer
in a context switch.

For normal LBRs, a context switch can flip the address space and LBR
entries are not tagged with an identifier, we need to wipe the LBR, even
for per-cpu events.

For LBR callstack, save/restore the stack is required during a context
switch.

Set PERF_ATTACH_SCHED_CB for the event with large PEBS & LBR.

Fixes: 9c964efa ("perf/x86/intel: Drain the PEBS buffer during context switches")
Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Link: https://lkml.kernel.org/r/20201130193842.10569-2-kan.liang@linux.intel.com
parent a5398bff

arch/x86/events/intel/core.c

+4 −1
Original line number Diff line number Diff line
@@ -3662,8 +3662,10 @@ static int intel_pmu_hw_config(struct perf_event *event) 
		if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {

			event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;

			if (!(event->attr.sample_type &

			      ~intel_pmu_large_pebs_flags(event)))

			      ~intel_pmu_large_pebs_flags(event))) {

				event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;

				event->attach_state |= PERF_ATTACH_SCHED_CB;

			}

		}

		if (x86_pmu.pebs_aliases)

			x86_pmu.pebs_aliases(event);
@@ -3676,6 +3678,7 @@ static int intel_pmu_hw_config(struct perf_event *event) 
		ret = intel_pmu_setup_lbr_filter(event);

		if (ret)

			return ret;

		event->attach_state |= PERF_ATTACH_SCHED_CB;



		/*

		 * BTS is set up earlier in this path, so don't account twice