Commit af8352f1 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge tag 'drm-msm-next-2021-04-11' of https://gitlab.freedesktop.org/drm/msm into drm-next 



msm-next from Rob:
* Big DSI phy/pll cleanup. Includes some clk patches, acked by
  maintainer
* Initial support for sc7280
* compatibles fixes for sm8150/sm8250
* cleanups for all dpu gens to use same bandwidth scaling paths (\o/)
* various shrinker path lock contention optimizations
* unpin/swap support for GEM objects (disabled by default, enable with
  msm.enable_eviction=1 .. due to various combinations of iommu drivers
  with older gens I want to get more testing on hw I don't have in front
  of me before enabling by default)
* The usual assortment of misc fixes and cleanups

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvL=4aw15qoY8fbKG9FCgnx8Y-dCtf7xiFwTQSHopwSQg@mail.gmail.com
parents 213cc929 a29c8c02

drivers/clk/clk-mux.c

+35 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
 */



#include <linux/clk-provider.h>

#include <linux/device.h>

#include <linux/module.h>

#include <linux/slab.h>

#include <linux/io.h>
@@ -206,6 +207,40 @@ struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, 
}

EXPORT_SYMBOL_GPL(__clk_hw_register_mux);



static void devm_clk_hw_release_mux(struct device *dev, void *res)

{

	clk_hw_unregister_mux(*(struct clk_hw **)res);

}



struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,

		const char *name, u8 num_parents,

		const char * const *parent_names,

		const struct clk_hw **parent_hws,

		const struct clk_parent_data *parent_data,

		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,

		u8 clk_mux_flags, u32 *table, spinlock_t *lock)

{

	struct clk_hw **ptr, *hw;



	ptr = devres_alloc(devm_clk_hw_release_mux, sizeof(*ptr), GFP_KERNEL);

	if (!ptr)

		return ERR_PTR(-ENOMEM);



	hw = __clk_hw_register_mux(dev, np, name, num_parents, parent_names, parent_hws,

				       parent_data, flags, reg, shift, mask,

				       clk_mux_flags, table, lock);



	if (!IS_ERR(hw)) {

		*ptr = hw;

		devres_add(dev, ptr);

	} else {

		devres_free(ptr);

	}



	return hw;

}

EXPORT_SYMBOL_GPL(__devm_clk_hw_register_mux);



struct clk *clk_register_mux_table(struct device *dev, const char *name,

		const char * const *parent_names, u8 num_parents,

		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,

drivers/gpu/drm/msm/Kconfig

+1 −8
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ config DRM_MSM 
	select SND_SOC_HDMI_CODEC if SND_SOC

	select SYNC_FILE

	select PM_OPP

	select NVMEM

	help

	  DRM/KMS driver for MSM/snapdragon.
@@ -76,14 +77,6 @@ config DRM_MSM_DSI 
	  Choose this option if you have a need for MIPI DSI connector

	  support.



config DRM_MSM_DSI_PLL

	bool "Enable DSI PLL driver in MSM DRM"

	depends on DRM_MSM_DSI && COMMON_CLK

	default y

	help

	  Choose this option to enable DSI PLL driver which provides DSI

	  source clocks under common clock framework.



config DRM_MSM_DSI_28NM_PHY

	bool "Enable DSI 28nm PHY driver in MSM DRM"

	depends on DRM_MSM_DSI

drivers/gpu/drm/msm/Makefile

+0 −9
Original line number Diff line number Diff line
@@ -136,13 +136,4 @@ msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o 
msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o

msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o



ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y)

msm-y += dsi/pll/dsi_pll.o

msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o

msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o

msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/pll/dsi_pll_14nm.o

msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/pll/dsi_pll_10nm.o

msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/pll/dsi_pll_7nm.o

endif



obj-$(CONFIG_DRM_MSM)	+= msm.o

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+9 −3
Original line number Diff line number Diff line
@@ -246,7 +246,7 @@ static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 
}



struct a6xx_gmu_oob_bits {

	int set, ack, set_new, ack_new;

	int set, ack, set_new, ack_new, clear, clear_new;

	const char *name;

};
@@ -260,6 +260,8 @@ static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = { 
		.ack = 24,

		.set_new = 30,

		.ack_new = 31,

		.clear = 24,

		.clear_new = 31,

	},



	[GMU_OOB_PERFCOUNTER_SET] = {
@@ -268,18 +270,22 @@ static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = { 
		.ack = 25,

		.set_new = 28,

		.ack_new = 30,

		.clear = 25,

		.clear_new = 29,

	},



	[GMU_OOB_BOOT_SLUMBER] = {

		.name = "BOOT_SLUMBER",

		.set = 22,

		.ack = 30,

		.clear = 30,

	},



	[GMU_OOB_DCVS_SET] = {

		.name = "GPU_DCVS",

		.set = 23,

		.ack = 31,

		.clear = 31,

	},

};
@@ -335,9 +341,9 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 
		return;



	if (gmu->legacy)

		bit = a6xx_gmu_oob_bits[state].ack;

		bit = a6xx_gmu_oob_bits[state].clear;

	else

		bit = a6xx_gmu_oob_bits[state].ack_new;

		bit = a6xx_gmu_oob_bits[state].clear_new;



	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);

}

drivers/gpu/drm/msm/adreno/adreno_gpu.c

+3 −0
Original line number Diff line number Diff line
@@ -273,6 +273,9 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) 
	case MSM_PARAM_FAULTS:

		*value = gpu->global_faults;

		return 0;

	case MSM_PARAM_SUSPENDS:

		*value = gpu->suspend_count;

		return 0;

	default:

		DBG("%s: invalid param: %u", gpu->name, param);

		return -EINVAL;