Commit af1e2cff authored by Paolo Abeni's avatar Paolo Abeni
Browse files

Merge branch 'add-a-driver-for-the-marvell-88q2110-phy' 

Stefan Eichenberger says:

====================
Add a driver for the Marvell 88Q2110 PHY

Add support for 1000BASE-T1 to the phy-c45 helper and add a first
1000BASE-T1 driver for the Marvell 88Q2110 PHY.
====================

Link: https://lore.kernel.org/r/20230719064258.9746-1-eichest@gmail.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parents cf3e913b 00f11ac7

drivers/net/phy/Kconfig

+6 −0
Original line number Diff line number Diff line
@@ -217,6 +217,12 @@ config MARVELL_10G_PHY 
	help

	  Support for the Marvell Alaska MV88X3310 and compatible PHYs.



config MARVELL_88Q2XXX_PHY

	tristate "Marvell 88Q2XXX PHY"

	help

	  Support for the Marvell 88Q2XXX 100/1000BASE-T1 Automotive Ethernet

	  PHYs.



config MARVELL_88X2222_PHY

	tristate "Marvell 88X2222 PHY"

	help

drivers/net/phy/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o 
obj-$(CONFIG_LXT_PHY)		+= lxt.o

obj-$(CONFIG_MARVELL_10G_PHY)	+= marvell10g.o

obj-$(CONFIG_MARVELL_PHY)	+= marvell.o

obj-$(CONFIG_MARVELL_88Q2XXX_PHY)	+= marvell-88q2xxx.o

obj-$(CONFIG_MARVELL_88X2222_PHY)	+= marvell-88x2222.o

obj-$(CONFIG_MAXLINEAR_GPHY)	+= mxl-gpy.o

obj-$(CONFIG_MEDIATEK_GE_PHY)	+= mediatek-ge.o

drivers/net/phy/marvell-88q2xxx.c

0 → 100644
+263 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Marvell 88Q2XXX automotive 100BASE-T1/1000BASE-T1 PHY driver

 */

#include <linux/ethtool_netlink.h>

#include <linux/marvell_phy.h>

#include <linux/phy.h>



#define MDIO_MMD_AN_MV_STAT			32769

#define MDIO_MMD_AN_MV_STAT_ANEG		0x0100

#define MDIO_MMD_AN_MV_STAT_LOCAL_RX		0x1000

#define MDIO_MMD_AN_MV_STAT_REMOTE_RX		0x2000

#define MDIO_MMD_AN_MV_STAT_LOCAL_MASTER	0x4000

#define MDIO_MMD_AN_MV_STAT_MS_CONF_FAULT	0x8000



#define MDIO_MMD_PCS_MV_100BT1_STAT1			33032

#define MDIO_MMD_PCS_MV_100BT1_STAT1_IDLE_ERROR	0x00FF

#define MDIO_MMD_PCS_MV_100BT1_STAT1_JABBER		0x0100

#define MDIO_MMD_PCS_MV_100BT1_STAT1_LINK		0x0200

#define MDIO_MMD_PCS_MV_100BT1_STAT1_LOCAL_RX		0x1000

#define MDIO_MMD_PCS_MV_100BT1_STAT1_REMOTE_RX		0x2000

#define MDIO_MMD_PCS_MV_100BT1_STAT1_LOCAL_MASTER	0x4000



#define MDIO_MMD_PCS_MV_100BT1_STAT2		33033

#define MDIO_MMD_PCS_MV_100BT1_STAT2_JABBER	0x0001

#define MDIO_MMD_PCS_MV_100BT1_STAT2_POL	0x0002

#define MDIO_MMD_PCS_MV_100BT1_STAT2_LINK	0x0004

#define MDIO_MMD_PCS_MV_100BT1_STAT2_ANGE	0x0008



static int mv88q2xxx_soft_reset(struct phy_device *phydev)

{

	int ret;

	int val;



	ret = phy_write_mmd(phydev, MDIO_MMD_PCS,

			    MDIO_PCS_1000BT1_CTRL, MDIO_PCS_1000BT1_CTRL_RESET);

	if (ret < 0)

		return ret;



	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,

					 MDIO_PCS_1000BT1_CTRL, val,

					 !(val & MDIO_PCS_1000BT1_CTRL_RESET),

					 50000, 600000, true);

}



static int mv88q2xxx_read_link_gbit(struct phy_device *phydev)

{

	int ret;

	bool link = false;



	/* Read vendor specific Auto-Negotiation status register to get local

	 * and remote receiver status according to software initialization

	 * guide.

	 */

	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_MMD_AN_MV_STAT);

	if (ret < 0) {

		return ret;

	} else if ((ret & MDIO_MMD_AN_MV_STAT_LOCAL_RX) &&

		   (ret & MDIO_MMD_AN_MV_STAT_REMOTE_RX)) {

		/* The link state is latched low so that momentary link

		 * drops can be detected. Do not double-read the status

		 * in polling mode to detect such short link drops except

		 * the link was already down.

		 */

		if (!phy_polling_mode(phydev) || !phydev->link) {

			ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_1000BT1_STAT);

			if (ret < 0)

				return ret;

			else if (ret & MDIO_PCS_1000BT1_STAT_LINK)

				link = true;

		}



		if (!link) {

			ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_1000BT1_STAT);

			if (ret < 0)

				return ret;

			else if (ret & MDIO_PCS_1000BT1_STAT_LINK)

				link = true;

		}

	}



	phydev->link = link;



	return 0;

}



static int mv88q2xxx_read_link_100m(struct phy_device *phydev)

{

	int ret;



	/* The link state is latched low so that momentary link

	 * drops can be detected. Do not double-read the status

	 * in polling mode to detect such short link drops except

	 * the link was already down. In case we are not polling,

	 * we always read the realtime status.

	 */

	if (!phy_polling_mode(phydev) || !phydev->link) {

		ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_MMD_PCS_MV_100BT1_STAT1);

		if (ret < 0)

			return ret;

		else if (ret & MDIO_MMD_PCS_MV_100BT1_STAT1_LINK)

			goto out;

	}



	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_MMD_PCS_MV_100BT1_STAT1);

	if (ret < 0)

		return ret;



out:

	/* Check if we have link and if the remote and local receiver are ok */

	if ((ret & MDIO_MMD_PCS_MV_100BT1_STAT1_LINK) &&

	    (ret & MDIO_MMD_PCS_MV_100BT1_STAT1_LOCAL_RX) &&

	    (ret & MDIO_MMD_PCS_MV_100BT1_STAT1_REMOTE_RX))

		phydev->link = true;

	else

		phydev->link = false;



	return 0;

}



static int mv88q2xxx_read_link(struct phy_device *phydev)

{

	int ret;



	/* The 88Q2XXX PHYs do not have the PMA/PMD status register available,

	 * therefore we need to read the link status from the vendor specific

	 * registers depending on the speed.

	 */

	if (phydev->speed == SPEED_1000)

		ret = mv88q2xxx_read_link_gbit(phydev);

	else

		ret = mv88q2xxx_read_link_100m(phydev);



	return ret;

}



static int mv88q2xxx_read_status(struct phy_device *phydev)

{

	int ret;



	ret = mv88q2xxx_read_link(phydev);

	if (ret < 0)

		return ret;



	return genphy_c45_read_pma(phydev);

}



static int mv88q2xxx_get_features(struct phy_device *phydev)

{

	int ret;



	ret = genphy_c45_pma_read_abilities(phydev);

	if (ret)

		return ret;



	/* We need to read the baset1 extended abilities manually because the

	 * PHY does not signalize it has the extended abilities register

	 * available.

	 */

	ret = genphy_c45_pma_baset1_read_abilities(phydev);

	if (ret)

		return ret;



	/* The PHY signalizes it supports autonegotiation. Unfortunately, so

	 * far it was not possible to get a link even when following the init

	 * sequence provided by Marvell. Disable it for now until a proper

	 * workaround is found or a new PHY revision is released.

	 */

	linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);



	return 0;

}



static int mv88q2xxx_config_aneg(struct phy_device *phydev)

{

	int ret;



	ret = genphy_c45_config_aneg(phydev);

	if (ret)

		return ret;



	return mv88q2xxx_soft_reset(phydev);

}



static int mv88q2xxx_config_init(struct phy_device *phydev)

{

	int ret;



	/* The 88Q2XXX PHYs do have the extended ability register available, but

	 * register MDIO_PMA_EXTABLE where they should signalize it does not

	 * work according to specification. Therefore, we force it here.

	 */

	phydev->pma_extable = MDIO_PMA_EXTABLE_BT1;



	/* Read the current PHY configuration */

	ret = genphy_c45_read_pma(phydev);

	if (ret)

		return ret;



	return mv88q2xxx_config_aneg(phydev);

}



static int mv88q2xxxx_get_sqi(struct phy_device *phydev)

{

	int ret;



	if (phydev->speed == SPEED_100) {

		/* Read the SQI from the vendor specific receiver status

		 * register

		 */

		ret = phy_read_mmd(phydev, MDIO_MMD_PCS, 0x8230);

		if (ret < 0)

			return ret;



		ret = ret >> 12;

	} else {

		/* Read from vendor specific registers, they are not documented

		 * but can be found in the Software Initialization Guide. Only

		 * revisions >= A0 are supported.

		 */

		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 0xFC5D, 0x00FF, 0x00AC);

		if (ret < 0)

			return ret;



		ret = phy_read_mmd(phydev, MDIO_MMD_PCS, 0xfc88);

		if (ret < 0)

			return ret;

	}



	return ret & 0x0F;

}



static int mv88q2xxxx_get_sqi_max(struct phy_device *phydev)

{

	return 15;

}



static struct phy_driver mv88q2xxx_driver[] = {

	{

		.phy_id			= MARVELL_PHY_ID_88Q2110,

		.phy_id_mask		= MARVELL_PHY_ID_MASK,

		.name			= "mv88q2110",

		.get_features		= mv88q2xxx_get_features,

		.config_aneg		= mv88q2xxx_config_aneg,

		.config_init		= mv88q2xxx_config_init,

		.read_status		= mv88q2xxx_read_status,

		.soft_reset		= mv88q2xxx_soft_reset,

		.set_loopback		= genphy_c45_loopback,

		.get_sqi		= mv88q2xxxx_get_sqi,

		.get_sqi_max		= mv88q2xxxx_get_sqi_max,

	},

};



module_phy_driver(mv88q2xxx_driver);



static struct mdio_device_id __maybe_unused mv88q2xxx_tbl[] = {

	{ MARVELL_PHY_ID_88Q2110, MARVELL_PHY_ID_MASK },

	{ /*sentinel*/ }

};

MODULE_DEVICE_TABLE(mdio, mv88q2xxx_tbl);



MODULE_DESCRIPTION("Marvell 88Q2XXX 100/1000BASE-T1 Automotive Ethernet PHY driver");

MODULE_LICENSE("GPL");

drivers/net/phy/phy-c45.c

+49 −14
Original line number Diff line number Diff line
@@ -108,7 +108,7 @@ EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_setup_master_slave); 
 */

int genphy_c45_pma_setup_forced(struct phy_device *phydev)

{

	int ctrl1, ctrl2, ret;

	int bt1_ctrl, ctrl1, ctrl2, ret;



	/* Half duplex is not supported */

	if (phydev->duplex != DUPLEX_FULL)
@@ -176,6 +176,15 @@ int genphy_c45_pma_setup_forced(struct phy_device *phydev) 
		ret = genphy_c45_pma_baset1_setup_master_slave(phydev);

		if (ret < 0)

			return ret;



		bt1_ctrl = 0;

		if (phydev->speed == SPEED_1000)

			bt1_ctrl = MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000;



		ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,

				     MDIO_PMA_PMD_BT1_CTRL_STRAP, bt1_ctrl);

		if (ret < 0)

			return ret;

	}



	return genphy_c45_an_disable_aneg(phydev);
@@ -872,6 +881,44 @@ int genphy_c45_an_config_eee_aneg(struct phy_device *phydev) 
	return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee);

}



/**

 * genphy_c45_pma_baset1_read_abilities - read supported baset1 link modes from PMA

 * @phydev: target phy_device struct

 *

 * Read the supported link modes from the extended BASE-T1 ability register

 */

int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev)

{

	int val;



	val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1);

	if (val < 0)

		return val;



	linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,

			 phydev->supported,

			 val & MDIO_PMA_PMD_BT1_B10L_ABLE);



	linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT,

			 phydev->supported,

			 val & MDIO_PMA_PMD_BT1_B100_ABLE);



	linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT,

			 phydev->supported,

			 val & MDIO_PMA_PMD_BT1_B1000_ABLE);



	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);

	if (val < 0)

		return val;



	linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,

			 phydev->supported,

			 val & MDIO_AN_STAT1_ABLE);



	return 0;

}

EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_abilities);



/**

 * genphy_c45_pma_read_abilities - read supported link modes from PMA

 * @phydev: target phy_device struct
@@ -968,21 +1015,9 @@ int genphy_c45_pma_read_abilities(struct phy_device *phydev) 
		}



		if (val & MDIO_PMA_EXTABLE_BT1) {

			val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1);

			val = genphy_c45_pma_baset1_read_abilities(phydev);

			if (val < 0)

				return val;



			linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,

					 phydev->supported,

					 val & MDIO_PMA_PMD_BT1_B10L_ABLE);



			val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);

			if (val < 0)

				return val;



			linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,

					 phydev->supported,

					 val & MDIO_AN_STAT1_ABLE);

		}

	}

include/linux/marvell_phy.h

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#define MARVELL_PHY_ID_88X3310		0x002b09a0

#define MARVELL_PHY_ID_88E2110		0x002b09b0

#define MARVELL_PHY_ID_88X2222		0x01410f10

#define MARVELL_PHY_ID_88Q2110		0x002b0980



/* Marvel 88E1111 in Finisar SFP module with modified PHY ID */

#define MARVELL_PHY_ID_88E1111_FINISAR	0x01ff0cc0