Commit aef4226f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pm-5.14-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm 

Pull more power management updates from Rafael Wysocki:
 "These include cpufreq core simplifications and fixes, cpufreq driver
  updates, cpuidle driver update, a generic power domains (genpd)
  locking fix and a debug-related simplification of the PM core.

  Specifics:

   - Drop the ->stop_cpu() (not really useful) and ->resolve_freq()
     (unused) cpufreq driver callbacks and modify the users of the
     former accordingly (Viresh Kumar, Rafael Wysocki).

   - Add frequency invariance support to the ACPI CPPC cpufreq driver
     again along with the related fixes and cleanups (Viresh Kumar).

   - Update the Meditak, qcom and SCMI ARM cpufreq drivers (Fabien
     Parent, Seiya Wang, Sibi Sankar, Christophe JAILLET).

   - Rename black/white-lists in the DT cpufreq driver (Viresh Kumar).

   - Add generic performance domains support to the dvfs DT bindings
     (Sudeep Holla).

   - Refine locking in the generic power domains (genpd) support code to
     avoid lock dependency issues (Stephen Boyd).

   - Update the MSM and qcom ARM cpuidle drivers (Bartosz Dudziak).

   - Simplify the PM core debug code by using ktime_us_delta() to
     compute time interval lengths (Mark-PK Tsai)"

* tag 'pm-5.14-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (21 commits)
  PM: domains: Shrink locking area of the gpd_list_lock
  PM: sleep: Use ktime_us_delta() in initcall_debug_report()
  cpufreq: CPPC: Add support for frequency invariance
  arch_topology: Avoid use-after-free for scale_freq_data
  cpufreq: CPPC: Pass structure instance by reference
  cpufreq: CPPC: Fix potential memleak in cppc_cpufreq_cpu_init
  cpufreq: Remove ->resolve_freq()
  cpufreq: Reuse cpufreq_driver_resolve_freq() in __cpufreq_driver_target()
  cpufreq: Remove the ->stop_cpu() driver callback
  cpufreq: powernv: Migrate to ->exit() callback instead of ->stop_cpu()
  cpufreq: CPPC: Migrate to ->exit() callback instead of ->stop_cpu()
  cpufreq: intel_pstate: Combine ->stop_cpu() and ->offline()
  cpuidle: qcom: Add SPM register data for MSM8226
  dt-bindings: arm: msm: Add SAW2 for MSM8226
  dt-bindings: cpufreq: update cpu type and clock name for MT8173 SoC
  clk: mediatek: remove deprecated CLK_INFRA_CA57SEL for MT8173 SoC
  cpufreq: dt: Rename black/white-lists
  cpufreq: scmi: Fix an error message
  cpufreq: mediatek: add support for mt8365
  dt-bindings: dvfs: Add support for generic performance domains
  ...
parents c6e8c51f 843372db

Documentation/cpu-freq/cpu-drivers.rst

+0 −6
Original line number Original line Diff line number Diff line
@@ -58,9 +58,6 @@ And optionally 




 .driver_data - cpufreq driver specific data.

 .driver_data - cpufreq driver specific data.





 .resolve_freq - Returns the most appropriate frequency for a target

 frequency. Doesn't change the frequency though.



 .get_intermediate and target_intermediate - Used to switch to stable

 .get_intermediate and target_intermediate - Used to switch to stable

 frequency while changing CPU frequency.

 frequency while changing CPU frequency.
@@ -71,9 +68,6 @@ And optionally 
 .exit - A pointer to a per-policy cleanup function called during

 .exit - A pointer to a per-policy cleanup function called during

 CPU_POST_DEAD phase of cpu hotplug process.

 CPU_POST_DEAD phase of cpu hotplug process.





 .stop_cpu - A pointer to a per-policy stop function called during

 CPU_DOWN_PREPARE phase of cpu hotplug process.



 .suspend - A pointer to a per-policy suspend function which is called

 .suspend - A pointer to a per-policy suspend function which is called

 with interrupts disabled and _after_ the governor is stopped for the

 with interrupts disabled and _after_ the governor is stopped for the

 policy.

 policy.

Documentation/devicetree/bindings/arm/cpus.yaml

+7 −0
Original line number Original line Diff line number Diff line
@@ -257,6 +257,13 @@ properties: 




      where voltage is in V, frequency is in MHz.

      where voltage is in V, frequency is in MHz.





  performance-domains:

    maxItems: 1

    description:

      List of phandles and performance domain specifiers, as defined by

      bindings of the performance domain provider. See also

      dvfs/performance-domain.yaml.



  power-domains:

  power-domains:

    description:

    description:

      List of phandles and PM domain specifiers, as defined by bindings of the

      List of phandles and PM domain specifiers, as defined by bindings of the

Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt

+1 −0
Original line number Original line Diff line number Diff line
@@ -25,6 +25,7 @@ PROPERTIES 
			"qcom,saw2"

			"qcom,saw2"

		    A more specific value could be one of:

		    A more specific value could be one of:

			"qcom,apq8064-saw2-v1.1-cpu"

			"qcom,apq8064-saw2-v1.1-cpu"

			"qcom,msm8226-saw2-v2.1-cpu"

			"qcom,msm8974-saw2-v2.1-cpu"

			"qcom,msm8974-saw2-v2.1-cpu"

			"qcom,apq8084-saw2-v2.1-cpu"

			"qcom,apq8084-saw2-v2.1-cpu"

Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt

+4 −4
Original line number Original line Diff line number Diff line
@@ -202,11 +202,11 @@ Example 2 (MT8173 SoC): 




	cpu2: cpu@100 {

	cpu2: cpu@100 {

		device_type = "cpu";

		device_type = "cpu";

		compatible = "arm,cortex-a57";

		compatible = "arm,cortex-a72";

		reg = <0x100>;

		reg = <0x100>;

		enable-method = "psci";

		enable-method = "psci";

		cpu-idle-states = <&CPU_SLEEP_0>;

		cpu-idle-states = <&CPU_SLEEP_0>;

		clocks = <&infracfg CLK_INFRA_CA57SEL>,

		clocks = <&infracfg CLK_INFRA_CA72SEL>,

			 <&apmixedsys CLK_APMIXED_MAINPLL>;

			 <&apmixedsys CLK_APMIXED_MAINPLL>;

		clock-names = "cpu", "intermediate";

		clock-names = "cpu", "intermediate";

		operating-points-v2 = <&cpu_opp_table_b>;

		operating-points-v2 = <&cpu_opp_table_b>;
@@ -214,11 +214,11 @@ Example 2 (MT8173 SoC): 




	cpu3: cpu@101 {

	cpu3: cpu@101 {

		device_type = "cpu";

		device_type = "cpu";

		compatible = "arm,cortex-a57";

		compatible = "arm,cortex-a72";

		reg = <0x101>;

		reg = <0x101>;

		enable-method = "psci";

		enable-method = "psci";

		cpu-idle-states = <&CPU_SLEEP_0>;

		cpu-idle-states = <&CPU_SLEEP_0>;

		clocks = <&infracfg CLK_INFRA_CA57SEL>,

		clocks = <&infracfg CLK_INFRA_CA72SEL>,

			 <&apmixedsys CLK_APMIXED_MAINPLL>;

			 <&apmixedsys CLK_APMIXED_MAINPLL>;

		clock-names = "cpu", "intermediate";

		clock-names = "cpu", "intermediate";

		operating-points-v2 = <&cpu_opp_table_b>;

		operating-points-v2 = <&cpu_opp_table_b>;

Documentation/devicetree/bindings/dvfs/performance-domain.yaml

0 → 100644
+74 −0
Original line number Original line Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Generic performance domains



maintainers:

  - Sudeep Holla <sudeep.holla@arm.com>



description: |+

  This binding is intended for performance management of groups of devices or

  CPUs that run in the same performance domain. Performance domains must not

  be confused with power domains. A performance domain is defined by a set

  of devices that always have to run at the same performance level. For a given

  performance domain, there is a single point of control that affects all the

  devices in the domain, making it impossible to set the performance level of

  an individual device in the domain independently from other devices in

  that domain. For example, a set of CPUs that share a voltage domain, and

  have a common frequency control, is said to be in the same performance

  domain.



  This device tree binding can be used to bind performance domain consumer

  devices with their performance domains provided by performance domain

  providers. A performance domain provider can be represented by any node in

  the device tree and can provide one or more performance domains. A consumer

  node can refer to the provider by a phandle and a set of phandle arguments

  (so called performance domain specifiers) of length specified by the

  \#performance-domain-cells property in the performance domain provider node.



select: true



properties:

  "#performance-domain-cells":

    description:

      Number of cells in a performance domain specifier. Typically 0 for nodes

      representing a single performance domain and 1 for nodes providing

      multiple performance domains (e.g. performance controllers), but can be

      any value as specified by device tree binding documentation of particular

      provider.

    enum: [ 0, 1 ]



  performance-domains:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    maxItems: 1

    description:

      A phandle and performance domain specifier as defined by bindings of the

      performance controller/provider specified by phandle.



additionalProperties: true



examples:

  - |

    performance: performance-controller@12340000 {

        compatible = "qcom,cpufreq-hw";

        reg = <0x12340000 0x1000>;

        #performance-domain-cells = <1>;

    };



    // The node above defines a performance controller that is a performance

    // domain provider and expects one cell as its phandle argument.



    cpus {

        #address-cells = <2>;

        #size-cells = <0>;



        cpu@0 {

            device_type = "cpu";

            compatible = "arm,cortex-a57";

            reg = <0x0 0x0>;

            performance-domains = <&performance 1>;

        };

    };