Commit aed1a2a5 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'thunderbolt-for-v6.5-rc1' of... 

Merge tag 'thunderbolt-for-v6.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt into usb-next

Mika writes:

thunderbolt: Changes for v6.5 merge window

This includes following Thunderbolt/USB4 changes for the v6.5 merge
window:

  - Improve debug logging
  - Rework for TMU and CL states handling
  - Retimer access improvements
  - Initial support for USB4 v2 features:

    * 80G symmetric link support
    * New notifications
    * PCIe extended encapsulation
    * enhanced uni-directional TMU mode
    * CL2 link low power state
    * DisplayPort 2.x tunneling

  - Support for Intel Barlow Ridge Thunderbolt/USB4 controller
  - Minor fixes and improvements.

All these have been in linux-next with no reported issues.

* tag 'thunderbolt-for-v6.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt: (55 commits)
  thunderbolt: Add test case for 3 DisplayPort tunnels
  thunderbolt: Add DisplayPort 2.x tunneling support
  thunderbolt: Make bandwidth allocation mode function names consistent
  thunderbolt: Enable CL2 low power state
  thunderbolt: Add support for enhanced uni-directional TMU mode
  thunderbolt: Increase NVM_MAX_SIZE to support Intel Barlow Ridge controller
  thunderbolt: Move constants related to NVM into nvm.c
  thunderbolt: Limit Intel Barlow Ridge USB3 bandwidth
  thunderbolt: Add Intel Barlow Ridge PCI ID
  thunderbolt: Fix PCIe adapter capability length for USB4 v2 routers
  thunderbolt: Fix DisplayPort IN adapter capability length for USB4 v2 routers
  thunderbolt: Add two additional double words for adapters TMU for USB4 v2 routers
  thunderbolt: Enable USB4 v2 PCIe TLP/DLLP extended encapsulation
  thunderbolt: Announce USB4 v2 connection manager support
  thunderbolt: Reset USB4 v2 host router
  thunderbolt: Add the new USB4 v2 notification types
  thunderbolt: Add support for USB4 v2 80 Gb/s link
  thunderbolt: Identify USB4 v2 routers
  thunderbolt: Do not touch lane 1 adapter path config space
  thunderbolt: Ignore data CRC mismatch for USB4 routers
  ...
parents 99f2d956 481012b4

drivers/thunderbolt/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
obj-${CONFIG_USB4} := thunderbolt.o

thunderbolt-objs := nhi.o nhi_ops.o ctl.o tb.o switch.o cap.o path.o tunnel.o eeprom.o

thunderbolt-objs += domain.o dma_port.o icm.o property.o xdomain.o lc.o tmu.o usb4.o

thunderbolt-objs += usb4_port.o nvm.o retimer.o quirks.o

thunderbolt-objs += usb4_port.o nvm.o retimer.o quirks.o clx.o



thunderbolt-${CONFIG_ACPI} += acpi.o

thunderbolt-$(CONFIG_DEBUG_FS) += debugfs.o

drivers/thunderbolt/acpi.c

+2 −3
Original line number Diff line number Diff line
@@ -296,16 +296,15 @@ static bool tb_acpi_bus_match(struct device *dev) 


static struct acpi_device *tb_acpi_switch_find_companion(struct tb_switch *sw)

{

	struct tb_switch *parent_sw = tb_switch_parent(sw);

	struct acpi_device *adev = NULL;

	struct tb_switch *parent_sw;



	/*

	 * Device routers exists under the downstream facing USB4 port

	 * of the parent router. Their _ADR is always 0.

	 */

	parent_sw = tb_switch_parent(sw);

	if (parent_sw) {

		struct tb_port *port = tb_port_at(tb_route(sw), parent_sw);

		struct tb_port *port = tb_switch_downstream_port(sw);

		struct acpi_device *port_adev;



		port_adev = acpi_find_child_by_adr(ACPI_COMPANION(&parent_sw->dev),

drivers/thunderbolt/clx.c

0 → 100644
+423 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * CLx support

 *

 * Copyright (C) 2020 - 2023, Intel Corporation

 * Authors: Gil Fine <gil.fine@intel.com>

 *	    Mika Westerberg <mika.westerberg@linux.intel.com>

 */



#include <linux/module.h>



#include "tb.h"



static bool clx_enabled = true;

module_param_named(clx, clx_enabled, bool, 0444);

MODULE_PARM_DESC(clx, "allow low power states on the high-speed lanes (default: true)");



static const char *clx_name(unsigned int clx)

{

	switch (clx) {

	case TB_CL0S | TB_CL1 | TB_CL2:

		return "CL0s/CL1/CL2";

	case TB_CL1 | TB_CL2:

		return "CL1/CL2";

	case TB_CL0S | TB_CL2:

		return "CL0s/CL2";

	case TB_CL0S | TB_CL1:

		return "CL0s/CL1";

	case TB_CL0S:

		return "CL0s";

	case 0:

		return "disabled";

	default:

		return "unknown";

	}

}



static int tb_port_pm_secondary_set(struct tb_port *port, bool secondary)

{

	u32 phy;

	int ret;



	ret = tb_port_read(port, &phy, TB_CFG_PORT,

			   port->cap_phy + LANE_ADP_CS_1, 1);

	if (ret)

		return ret;



	if (secondary)

		phy |= LANE_ADP_CS_1_PMS;

	else

		phy &= ~LANE_ADP_CS_1_PMS;



	return tb_port_write(port, &phy, TB_CFG_PORT,

			     port->cap_phy + LANE_ADP_CS_1, 1);

}



static int tb_port_pm_secondary_enable(struct tb_port *port)

{

	return tb_port_pm_secondary_set(port, true);

}



static int tb_port_pm_secondary_disable(struct tb_port *port)

{

	return tb_port_pm_secondary_set(port, false);

}



/* Called for USB4 or Titan Ridge routers only */

static bool tb_port_clx_supported(struct tb_port *port, unsigned int clx)

{

	u32 val, mask = 0;

	bool ret;



	/* Don't enable CLx in case of two single-lane links */

	if (!port->bonded && port->dual_link_port)

		return false;



	/* Don't enable CLx in case of inter-domain link */

	if (port->xdomain)

		return false;



	if (tb_switch_is_usb4(port->sw)) {

		if (!usb4_port_clx_supported(port))

			return false;

	} else if (!tb_lc_is_clx_supported(port)) {

		return false;

	}



	if (clx & TB_CL0S)

		mask |= LANE_ADP_CS_0_CL0S_SUPPORT;

	if (clx & TB_CL1)

		mask |= LANE_ADP_CS_0_CL1_SUPPORT;

	if (clx & TB_CL2)

		mask |= LANE_ADP_CS_0_CL2_SUPPORT;



	ret = tb_port_read(port, &val, TB_CFG_PORT,

			   port->cap_phy + LANE_ADP_CS_0, 1);

	if (ret)

		return false;



	return !!(val & mask);

}



static int tb_port_clx_set(struct tb_port *port, unsigned int clx, bool enable)

{

	u32 phy, mask = 0;

	int ret;



	if (clx & TB_CL0S)

		mask |= LANE_ADP_CS_1_CL0S_ENABLE;

	if (clx & TB_CL1)

		mask |= LANE_ADP_CS_1_CL1_ENABLE;

	if (clx & TB_CL2)

		mask |= LANE_ADP_CS_1_CL2_ENABLE;



	if (!mask)

		return -EOPNOTSUPP;



	ret = tb_port_read(port, &phy, TB_CFG_PORT,

			   port->cap_phy + LANE_ADP_CS_1, 1);

	if (ret)

		return ret;



	if (enable)

		phy |= mask;

	else

		phy &= ~mask;



	return tb_port_write(port, &phy, TB_CFG_PORT,

			     port->cap_phy + LANE_ADP_CS_1, 1);

}



static int tb_port_clx_disable(struct tb_port *port, unsigned int clx)

{

	return tb_port_clx_set(port, clx, false);

}



static int tb_port_clx_enable(struct tb_port *port, unsigned int clx)

{

	return tb_port_clx_set(port, clx, true);

}



static int tb_port_clx(struct tb_port *port)

{

	u32 val;

	int ret;



	if (!tb_port_clx_supported(port, TB_CL0S | TB_CL1 | TB_CL2))

		return 0;



	ret = tb_port_read(port, &val, TB_CFG_PORT,

			   port->cap_phy + LANE_ADP_CS_1, 1);

	if (ret)

		return ret;



	if (val & LANE_ADP_CS_1_CL0S_ENABLE)

		ret |= TB_CL0S;

	if (val & LANE_ADP_CS_1_CL1_ENABLE)

		ret |= TB_CL1;

	if (val & LANE_ADP_CS_1_CL2_ENABLE)

		ret |= TB_CL2;



	return ret;

}



/**

 * tb_port_clx_is_enabled() - Is given CL state enabled

 * @port: USB4 port to check

 * @clx: Mask of CL states to check

 *

 * Returns true if any of the given CL states is enabled for @port.

 */

bool tb_port_clx_is_enabled(struct tb_port *port, unsigned int clx)

{

	return !!(tb_port_clx(port) & clx);

}



/**

 * tb_switch_clx_init() - Initialize router CL states

 * @sw: Router

 *

 * Can be called for any router. Initializes the current CL state by

 * reading it from the hardware.

 *

 * Returns %0 in case of success and negative errno in case of failure.

 */

int tb_switch_clx_init(struct tb_switch *sw)

{

	struct tb_port *up, *down;

	unsigned int clx, tmp;



	if (tb_switch_is_icm(sw))

		return 0;



	if (!tb_route(sw))

		return 0;



	if (!tb_switch_clx_is_supported(sw))

		return 0;



	up = tb_upstream_port(sw);

	down = tb_switch_downstream_port(sw);



	clx = tb_port_clx(up);

	tmp = tb_port_clx(down);

	if (clx != tmp)

		tb_sw_warn(sw, "CLx: inconsistent configuration %#x != %#x\n",

			   clx, tmp);



	tb_sw_dbg(sw, "CLx: current mode: %s\n", clx_name(clx));



	sw->clx = clx;

	return 0;

}



static int tb_switch_pm_secondary_resolve(struct tb_switch *sw)

{

	struct tb_port *up, *down;

	int ret;



	if (!tb_route(sw))

		return 0;



	up = tb_upstream_port(sw);

	down = tb_switch_downstream_port(sw);

	ret = tb_port_pm_secondary_enable(up);

	if (ret)

		return ret;



	return tb_port_pm_secondary_disable(down);

}



static int tb_switch_mask_clx_objections(struct tb_switch *sw)

{

	int up_port = sw->config.upstream_port_number;

	u32 offset, val[2], mask_obj, unmask_obj;

	int ret, i;



	/* Only Titan Ridge of pre-USB4 devices support CLx states */

	if (!tb_switch_is_titan_ridge(sw))

		return 0;



	if (!tb_route(sw))

		return 0;



	/*

	 * In Titan Ridge there are only 2 dual-lane Thunderbolt ports:

	 * Port A consists of lane adapters 1,2 and

	 * Port B consists of lane adapters 3,4

	 * If upstream port is A, (lanes are 1,2), we mask objections from

	 * port B (lanes 3,4) and unmask objections from Port A and vice-versa.

	 */

	if (up_port == 1) {

		mask_obj = TB_LOW_PWR_C0_PORT_B_MASK;

		unmask_obj = TB_LOW_PWR_C1_PORT_A_MASK;

		offset = TB_LOW_PWR_C1_CL1;

	} else {

		mask_obj = TB_LOW_PWR_C1_PORT_A_MASK;

		unmask_obj = TB_LOW_PWR_C0_PORT_B_MASK;

		offset = TB_LOW_PWR_C3_CL1;

	}



	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,

			 sw->cap_lp + offset, ARRAY_SIZE(val));

	if (ret)

		return ret;



	for (i = 0; i < ARRAY_SIZE(val); i++) {

		val[i] |= mask_obj;

		val[i] &= ~unmask_obj;

	}



	return tb_sw_write(sw, &val, TB_CFG_SWITCH,

			   sw->cap_lp + offset, ARRAY_SIZE(val));

}



/**

 * tb_switch_clx_is_supported() - Is CLx supported on this type of router

 * @sw: The router to check CLx support for

 */

bool tb_switch_clx_is_supported(const struct tb_switch *sw)

{

	if (!clx_enabled)

		return false;



	if (sw->quirks & QUIRK_NO_CLX)

		return false;



	/*

	 * CLx is not enabled and validated on Intel USB4 platforms

	 * before Alder Lake.

	 */

	if (tb_switch_is_tiger_lake(sw))

		return false;



	return tb_switch_is_usb4(sw) || tb_switch_is_titan_ridge(sw);

}



static bool validate_mask(unsigned int clx)

{

	/* Previous states need to be enabled */

	if (clx & TB_CL1)

		return (clx & TB_CL0S) == TB_CL0S;

	return true;

}



/**

 * tb_switch_clx_enable() - Enable CLx on upstream port of specified router

 * @sw: Router to enable CLx for

 * @clx: The CLx state to enable

 *

 * CLx is enabled only if both sides of the link support CLx, and if both sides

 * of the link are not configured as two single lane links and only if the link

 * is not inter-domain link. The complete set of conditions is described in CM

 * Guide 1.0 section 8.1.

 *

 * Returns %0 on success or an error code on failure.

 */

int tb_switch_clx_enable(struct tb_switch *sw, unsigned int clx)

{

	bool up_clx_support, down_clx_support;

	struct tb_switch *parent_sw;

	struct tb_port *up, *down;

	int ret;



	if (!clx || sw->clx == clx)

		return 0;



	if (!validate_mask(clx))

		return -EINVAL;



	parent_sw = tb_switch_parent(sw);

	if (!parent_sw)

		return 0;



	if (!tb_switch_clx_is_supported(parent_sw) ||

	    !tb_switch_clx_is_supported(sw))

		return 0;



	/* Only support CL2 for v2 routers */

	if ((clx & TB_CL2) &&

	    (usb4_switch_version(parent_sw) < 2 ||

	     usb4_switch_version(sw) < 2))

		return -EOPNOTSUPP;



	ret = tb_switch_pm_secondary_resolve(sw);

	if (ret)

		return ret;



	up = tb_upstream_port(sw);

	down = tb_switch_downstream_port(sw);



	up_clx_support = tb_port_clx_supported(up, clx);

	down_clx_support = tb_port_clx_supported(down, clx);



	tb_port_dbg(up, "CLx: %s %ssupported\n", clx_name(clx),

		    up_clx_support ? "" : "not ");

	tb_port_dbg(down, "CLx: %s %ssupported\n", clx_name(clx),

		    down_clx_support ? "" : "not ");



	if (!up_clx_support || !down_clx_support)

		return -EOPNOTSUPP;



	ret = tb_port_clx_enable(up, clx);

	if (ret)

		return ret;



	ret = tb_port_clx_enable(down, clx);

	if (ret) {

		tb_port_clx_disable(up, clx);

		return ret;

	}



	ret = tb_switch_mask_clx_objections(sw);

	if (ret) {

		tb_port_clx_disable(up, clx);

		tb_port_clx_disable(down, clx);

		return ret;

	}



	sw->clx |= clx;



	tb_sw_dbg(sw, "CLx: %s enabled\n", clx_name(clx));

	return 0;

}



/**

 * tb_switch_clx_disable() - Disable CLx on upstream port of specified router

 * @sw: Router to disable CLx for

 *

 * Disables all CL states of the given router. Can be called on any

 * router and if the states were not enabled already does nothing.

 *

 * Returns the CL states that were disabled or negative errno in case of

 * failure.

 */

int tb_switch_clx_disable(struct tb_switch *sw)

{

	unsigned int clx = sw->clx;

	struct tb_port *up, *down;

	int ret;



	if (!tb_switch_clx_is_supported(sw))

		return 0;



	if (!clx)

		return 0;



	up = tb_upstream_port(sw);

	down = tb_switch_downstream_port(sw);



	ret = tb_port_clx_disable(up, clx);

	if (ret)

		return ret;



	ret = tb_port_clx_disable(down, clx);

	if (ret)

		return ret;



	sw->clx = 0;



	tb_sw_dbg(sw, "CLx: %s disabled\n", clx_name(clx));

	return clx;

}

drivers/thunderbolt/ctl.c

+28 −0
Original line number Diff line number Diff line
@@ -409,6 +409,13 @@ static int tb_async_error(const struct ctl_pkg *pkg) 
	case TB_CFG_ERROR_HEC_ERROR_DETECTED:

	case TB_CFG_ERROR_FLOW_CONTROL_ERROR:

	case TB_CFG_ERROR_DP_BW:

	case TB_CFG_ERROR_ROP_CMPLT:

	case TB_CFG_ERROR_POP_CMPLT:

	case TB_CFG_ERROR_PCIE_WAKE:

	case TB_CFG_ERROR_DP_CON_CHANGE:

	case TB_CFG_ERROR_DPTX_DISCOVERY:

	case TB_CFG_ERROR_LINK_RECOVERY:

	case TB_CFG_ERROR_ASYM_LINK:

		return true;



	default:
@@ -758,6 +765,27 @@ int tb_cfg_ack_notification(struct tb_ctl *ctl, u64 route, 
	case TB_CFG_ERROR_DP_BW:

		name = "DP_BW";

		break;

	case TB_CFG_ERROR_ROP_CMPLT:

		name = "router operation completion";

		break;

	case TB_CFG_ERROR_POP_CMPLT:

		name = "port operation completion";

		break;

	case TB_CFG_ERROR_PCIE_WAKE:

		name = "PCIe wake";

		break;

	case TB_CFG_ERROR_DP_CON_CHANGE:

		name = "DP connector change";

		break;

	case TB_CFG_ERROR_DPTX_DISCOVERY:

		name = "DPTX discovery";

		break;

	case TB_CFG_ERROR_LINK_RECOVERY:

		name = "link recovery";

		break;

	case TB_CFG_ERROR_ASYM_LINK:

		name = "asymmetric link";

		break;

	default:

		name = "unknown";

		break;

drivers/thunderbolt/debugfs.c

+44 −20
Original line number Diff line number Diff line
@@ -14,12 +14,15 @@ 
#include "tb.h"

#include "sb_regs.h"



#define PORT_CAP_PCIE_LEN	1

#define PORT_CAP_V1_PCIE_LEN	1

#define PORT_CAP_V2_PCIE_LEN	2

#define PORT_CAP_POWER_LEN	2

#define PORT_CAP_LANE_LEN	3

#define PORT_CAP_USB3_LEN	5

#define PORT_CAP_DP_LEN		8

#define PORT_CAP_TMU_LEN	8

#define PORT_CAP_DP_V1_LEN	9

#define PORT_CAP_DP_V2_LEN	14

#define PORT_CAP_TMU_V1_LEN	8

#define PORT_CAP_TMU_V2_LEN	10

#define PORT_CAP_BASIC_LEN	9

#define PORT_CAP_USB4_LEN	20
@@ -553,8 +556,9 @@ static int margining_run_write(void *data, u64 val) 
	struct usb4_port *usb4 = port->usb4;

	struct tb_switch *sw = port->sw;

	struct tb_margining *margining;

	struct tb_switch *down_sw;

	struct tb *tb = sw->tb;

	int ret;

	int ret, clx;



	if (val != 1)

		return -EINVAL;
@@ -566,16 +570,25 @@ static int margining_run_write(void *data, u64 val) 
		goto out_rpm_put;

	}



	if (tb_is_upstream_port(port))

		down_sw = sw;

	else if (port->remote)

		down_sw = port->remote->sw;

	else

		down_sw = NULL;



	if (down_sw) {

		/*

	 * CL states may interfere with lane margining so inform the user know

	 * and bail out.

		 * CL states may interfere with lane margining so

		 * disable them temporarily now.

		 */

	if (tb_port_is_clx_enabled(port, TB_CL1 | TB_CL2)) {

		tb_port_warn(port,

			     "CL states are enabled, Disable them with clx=0 and re-connect\n");

		ret = -EINVAL;

		ret = tb_switch_clx_disable(down_sw);

		if (ret < 0) {

			tb_sw_warn(down_sw, "failed to disable CL states\n");

			goto out_unlock;

		}

		clx = ret;

	}



	margining = usb4->margining;
@@ -586,7 +599,7 @@ static int margining_run_write(void *data, u64 val) 
					  margining->right_high,

					  USB4_MARGIN_SW_COUNTER_CLEAR);

		if (ret)

			goto out_unlock;

			goto out_clx;



		ret = usb4_port_sw_margin_errors(port, &margining->results[0]);

	} else {
@@ -600,6 +613,9 @@ static int margining_run_write(void *data, u64 val) 
					  margining->right_high, margining->results);

	}



out_clx:

	if (down_sw)

		tb_switch_clx_enable(down_sw, clx);

out_unlock:

	mutex_unlock(&tb->lock);

out_rpm_put:
@@ -1148,7 +1164,10 @@ static void port_cap_show(struct tb_port *port, struct seq_file *s, 
		break;



	case TB_PORT_CAP_TIME1:

		length = PORT_CAP_TMU_LEN;

		if (usb4_switch_version(port->sw) < 2)

			length = PORT_CAP_TMU_V1_LEN;

		else

			length = PORT_CAP_TMU_V2_LEN;

		break;



	case TB_PORT_CAP_POWER:
@@ -1157,12 +1176,17 @@ static void port_cap_show(struct tb_port *port, struct seq_file *s, 


	case TB_PORT_CAP_ADAP:

		if (tb_port_is_pcie_down(port) || tb_port_is_pcie_up(port)) {

			length = PORT_CAP_PCIE_LEN;

		} else if (tb_port_is_dpin(port) || tb_port_is_dpout(port)) {

			if (usb4_dp_port_bw_mode_supported(port))

				length = PORT_CAP_DP_LEN + 1;

			if (usb4_switch_version(port->sw) < 2)

				length = PORT_CAP_V1_PCIE_LEN;

			else

				length = PORT_CAP_V2_PCIE_LEN;

		} else if (tb_port_is_dpin(port)) {

			if (usb4_switch_version(port->sw) < 2)

				length = PORT_CAP_DP_V1_LEN;

			else

				length = PORT_CAP_DP_LEN;

				length = PORT_CAP_DP_V2_LEN;

		} else if (tb_port_is_dpout(port)) {

			length = PORT_CAP_DP_V1_LEN;

		} else if (tb_port_is_usb3_down(port) ||

			   tb_port_is_usb3_up(port)) {

			length = PORT_CAP_USB3_LEN;