Commit aeb01e6d authored by Chen Yu's avatar Chen Yu Committed by Len Brown
Browse files

tools/power turbostat: Print the C-state Pre-wake settings

C-state pre-wake setting[1] is an optimization for some Intel CPUs to
be woken up from deep C-states in order to reduce latency. According to
the spec, the BIT30 is the C-state Pre-wake Disable. Expose this setting
accordingly.
Sample output from turbostat:
...
cpu51: MSR_IA32_POWER_CTL: 0x1a00a40059 (C1E auto-promotion: DISabled)
C-state Pre-wake: ENabled
cpu51: MSR_TURBO_RATIO_LIMIT: 0x2021212121212224
...

[1] https://intel.github.io/wult/#c-state-pre-wake



Signed-off-by: default avatarChen Yu <yu.c.chen@intel.com>
Signed-off-by: default avatarLen Brown <len.brown@intel.com>
parent 8c69da29
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+14 −0
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ double rapl_dram_energy_units, rapl_energy_units;
double rapl_joule_counter_range;
unsigned int do_core_perf_limit_reasons;
unsigned int has_automatic_cstate_conversion;
unsigned int dis_cstate_prewake;
unsigned int do_gfx_perf_limit_reasons;
unsigned int do_ring_perf_limit_reasons;
unsigned int crystal_hz;
@@ -2271,6 +2272,8 @@ calculate_tsc_tweak()
	tsc_tweak = base_hz / tsc_hz;
}

void prewake_cstate_probe(unsigned int family, unsigned int model);

static void
dump_nhm_platform_info(void)
{
@@ -2293,6 +2296,11 @@ dump_nhm_platform_info(void)
	fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
		base_cpu, msr, msr & 0x2 ? "EN" : "DIS");

	/* C-state Pre-wake Disable (CSTATE_PREWAKE_DISABLE) */
	if (dis_cstate_prewake)
		fprintf(outf, "C-state Pre-wake: %sabled\n",
			msr & 0x40000000 ? "DIS" : "EN");

	return;
}

@@ -4546,6 +4554,12 @@ void automatic_cstate_conversion_probe(unsigned int family, unsigned int model)
		has_automatic_cstate_conversion = 1;
}

void prewake_cstate_probe(unsigned int family, unsigned int model)
{
	if (is_icx(family, model))
		dis_cstate_prewake = 1;
}

int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
{
	unsigned long long msr;