Commit ae8373a5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_urgent_for_6.4-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fix from Dave Hansen:
 "This works around and issue where the INVLPG instruction may miss
  invalidating kernel TLB entries in recent hybrid CPUs.

  I do expect an eventual microcode fix for this. When the microcode
  version numbers are known, we can circle back around and add them the
  model table to disable this workaround"

* tag 'x86_urgent_for_6.4-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mm: Avoid incomplete Global INVLPG flushes
parents 1177dcc9 ce0b15d1

arch/x86/mm/init.c

+25 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/sched/task.h>



#include <asm/set_memory.h>

#include <asm/cpu_device_id.h>

#include <asm/e820/api.h>

#include <asm/init.h>

#include <asm/page.h>
@@ -261,6 +262,24 @@ static void __init probe_page_size_mask(void) 
	}

}



#define INTEL_MATCH(_model) { .vendor  = X86_VENDOR_INTEL,	\

			      .family  = 6,			\

			      .model = _model,			\

			    }

/*

 * INVLPG may not properly flush Global entries

 * on these CPUs when PCIDs are enabled.

 */

static const struct x86_cpu_id invlpg_miss_ids[] = {

	INTEL_MATCH(INTEL_FAM6_ALDERLAKE   ),

	INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ),

	INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ),

	INTEL_MATCH(INTEL_FAM6_RAPTORLAKE  ),

	INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P),

	INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S),

	{}

};



static void setup_pcid(void)

{

	if (!IS_ENABLED(CONFIG_X86_64))
@@ -269,6 +288,12 @@ static void setup_pcid(void) 
	if (!boot_cpu_has(X86_FEATURE_PCID))

		return;



	if (x86_match_cpu(invlpg_miss_ids)) {

		pr_info("Incomplete global flushes, disabling PCID");

		setup_clear_cpu_cap(X86_FEATURE_PCID);

		return;

	}



	if (boot_cpu_has(X86_FEATURE_PGE)) {

		/*

		 * This can't be cr4_set_bits_and_update_boot() -- the