Commit ae7322a0 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/pm' 

  - Check .bridge_d3() hook for NULL before calling it (Bjorn Helgaas)

  - Disable PME# for Pericom OHCI/UHCI USB controllers because it's
    not reliably asserted on USB hotplug (Kai-Heng Feng)

  - Assume ports without DLL Link Active train links in 100 ms to work
    around Thunderbolt bridge defects (Mika Westerberg)

* pci/pm:
  PCI/PM: Assume ports without DLL Link Active train links in 100 ms
  PCI/PM: Adjust pcie_wait_for_link_delay() for caller delay
  PCI: Avoid Pericom USB controller OHCI/EHCI PME# defect
  serial: 8250_pci: Move Pericom IDs to pci_ids.h
  PCI/PM: Call .bridge_d3() hook only if non-NULL
parents ff33cc2f ec411e02

drivers/pci/pci.c

+26 −12
Original line number Diff line number Diff line
@@ -844,7 +844,9 @@ static inline bool platform_pci_need_resume(struct pci_dev *dev) 


static inline bool platform_pci_bridge_d3(struct pci_dev *dev)

{

	return pci_platform_pm ? pci_platform_pm->bridge_d3(dev) : false;

	if (pci_platform_pm && pci_platform_pm->bridge_d3)

		return pci_platform_pm->bridge_d3(dev);

	return false;

}



/**
@@ -4636,7 +4638,8 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) 
 * pcie_wait_for_link_delay - Wait until link is active or inactive

 * @pdev: Bridge device

 * @active: waiting for active or inactive?

 * @delay: Delay to wait after link has become active (in ms)

 * @delay: Delay to wait after link has become active (in ms). Specify %0

 *	   for no delay.

 *

 * Use this to wait till link becomes active or inactive.

 */
@@ -4649,10 +4652,10 @@ static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, 


	/*

	 * Some controllers might not implement link active reporting. In this

	 * case, we wait for 1000 + 100 ms.

	 * case, we wait for 1000 ms + any delay requested by the caller.

	 */

	if (!pdev->link_active_reporting) {

		msleep(1100);

		msleep(timeout + delay);

		return true;

	}
@@ -4677,7 +4680,7 @@ static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, 
		msleep(10);

		timeout -= 10;

	}

	if (active && ret)

	if (active && ret && delay)

		msleep(delay);

	else if (ret != active)

		pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",
@@ -4798,17 +4801,28 @@ void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev) 
	if (!pcie_downstream_port(dev))

		return;



	if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {

		pci_dbg(dev, "waiting %d ms for downstream link\n", delay);

		msleep(delay);

	} else {

		pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",

			delay);

		if (!pcie_wait_for_link_delay(dev, true, delay)) {

	/*

	 * Per PCIe r5.0, sec 6.6.1, for downstream ports that support

	 * speeds > 5 GT/s, we must wait for link training to complete

	 * before the mandatory delay.

	 *

	 * We can only tell when link training completes via DLL Link

	 * Active, which is required for downstream ports that support

	 * speeds > 5 GT/s (sec 7.5.3.6).  Unfortunately some common

	 * devices do not implement Link Active reporting even when it's

	 * required, so we'll check for that directly instead of checking

	 * the supported link speed.  We assume devices without Link Active

	 * reporting can train in 100 ms regardless of speed.

	 */

	if (dev->link_active_reporting) {

		pci_dbg(dev, "waiting for link to train\n");

		if (!pcie_wait_for_link_delay(dev, true, 0)) {

			/* Did not train, no need to wait any further */

			return;

		}

	}

	pci_dbg(child, "waiting %d ms to become accessible\n", delay);

	msleep(delay);



	if (!pci_device_is_present(child)) {

		pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);

drivers/pci/quirks.c

+13 −0
Original line number Diff line number Diff line
@@ -5567,3 +5567,16 @@ static void pci_fixup_no_d0_pme(struct pci_dev *dev) 
	dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);



/*

 * Device [12d8:0x400e] and [12d8:0x400f]

 * These devices advertise PME# support in all power states but don't

 * reliably assert it.

 */

static void pci_fixup_no_pme(struct pci_dev *dev)

{

	pci_info(dev, "PME# is unreliable, disabling it\n");

	dev->pme_support = 0;

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_pme);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_pme);

drivers/tty/serial/8250/8250_pci.c

+0 −6
Original line number Diff line number Diff line
@@ -1869,12 +1869,6 @@ pci_moxa_setup(struct serial_private *priv, 
#define PCIE_DEVICE_ID_WCH_CH384_4S	0x3470

#define PCIE_DEVICE_ID_WCH_CH382_2S	0x3253



#define PCI_VENDOR_ID_PERICOM			0x12D8

#define PCI_DEVICE_ID_PERICOM_PI7C9X7951	0x7951

#define PCI_DEVICE_ID_PERICOM_PI7C9X7952	0x7952

#define PCI_DEVICE_ID_PERICOM_PI7C9X7954	0x7954

#define PCI_DEVICE_ID_PERICOM_PI7C9X7958	0x7958



#define PCI_VENDOR_ID_ACCESIO			0x494f

#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB	0x1051

#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S	0x1053

include/linux/pci_ids.h

+6 −0
Original line number Diff line number Diff line
@@ -1832,6 +1832,12 @@ 
#define PCI_VENDOR_ID_NVIDIA_SGS	0x12d2

#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018



#define PCI_VENDOR_ID_PERICOM			0x12D8

#define PCI_DEVICE_ID_PERICOM_PI7C9X7951	0x7951

#define PCI_DEVICE_ID_PERICOM_PI7C9X7952	0x7952

#define PCI_DEVICE_ID_PERICOM_PI7C9X7954	0x7954

#define PCI_DEVICE_ID_PERICOM_PI7C9X7958	0x7958



#define PCI_SUBVENDOR_ID_CHASE_PCIFAST		0x12E0

#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4		0x0031

#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8		0x0021