Commit ae64a141 authored by Tao Su's avatar Tao Su Committed by Quanxian Wang
Browse files

x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest 

mainline inclusion
from mainline-v6.13-rc1
commit a0423af92cb31e6fc4f53ef9b6e19fdf08ad4395
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/IBPCSD
CVE: N/A
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a0423af92cb31e6fc4f53ef9b6e19fdf08ad4395



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Intel-SIG: commit a0423af92cb3 ("x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest")

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x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest

Latest Intel platform Clearwater Forest has introduced new instructions
enumerated by CPUIDs of SHA512, SM3, SM4 and AVX-VNNI-INT16. Advertise
these CPUIDs to userspace so that guests can query them directly.

SHA512, SM3 and SM4 are on an expected-dense CPUID leaf and some other
bits on this leaf have kernel usages. Considering they have not truly
kernel usages, hide them in /proc/cpuinfo.

These new instructions only operate in xmm, ymm registers and have no new
VMX controls, so there is no additional host enabling required for guests
to use these instructions, i.e. advertising these CPUIDs to userspace is
safe.

Tested-by: default avatarJiaan Lu <jiaan.lu@intel.com>
Tested-by: default avatarXuelian Guo <xuelian.guo@intel.com>
Signed-off-by: default avatarTao Su <tao1.su@linux.intel.com>
Message-ID: <20241105054825.870939-1-tao1.su@linux.intel.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: default avatarQuanxian Wang <quanxian.wang@intel.com>
parent 6ae6aae4

arch/x86/include/asm/cpufeatures.h

+3 −0
Original line number Diff line number Diff line
@@ -337,6 +337,9 @@ 
#define X86_FEATURE_ZEN1		(11*32+31) /* "" CPU based on Zen1 microarchitecture */



/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

#define X86_FEATURE_SHA512		(12*32+ 0) /* SHA512 instructions */

#define X86_FEATURE_SM3			(12*32+ 1) /* SM3 instructions */

#define X86_FEATURE_SM4			(12*32+ 2) /* SM4 instructions */

#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */

#define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* "" CMPccXADD instructions */

arch/x86/kvm/cpuid.c

+5 −5
Original line number Diff line number Diff line
@@ -689,14 +689,14 @@ void kvm_set_cpu_caps(void) 
		kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);



	kvm_cpu_cap_mask(CPUID_7_1_EAX,

		F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) |

		F(FZRM) | F(FSRS) | F(FSRC) |

		F(AMX_FP16) | F(AVX_IFMA) | F(LAM)

		F(SHA512) | F(SM3) | F(SM4) | F(AVX_VNNI) | F(AVX512_BF16) |

		F(CMPCCXADD) | F(FZRM) | F(FSRS) | F(FSRC) | F(AMX_FP16) |

		F(AVX_IFMA) | F(LAM)

	);



	kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX,

		F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI) |

		F(AMX_COMPLEX)

		F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(AMX_COMPLEX) |

		F(AVX_VNNI_INT16) | F(PREFETCHITI)

	);



	kvm_cpu_cap_init_kvm_defined(CPUID_7_2_EDX,

arch/x86/kvm/reverse_cpuid.h

+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ enum kvm_only_cpuid_leafs { 
#define X86_FEATURE_AVX_VNNI_INT8       KVM_X86_FEATURE(CPUID_7_1_EDX, 4)

#define X86_FEATURE_AVX_NE_CONVERT      KVM_X86_FEATURE(CPUID_7_1_EDX, 5)

#define X86_FEATURE_AMX_COMPLEX         KVM_X86_FEATURE(CPUID_7_1_EDX, 8)

#define X86_FEATURE_AVX_VNNI_INT16      KVM_X86_FEATURE(CPUID_7_1_EDX, 10)

#define X86_FEATURE_PREFETCHITI         KVM_X86_FEATURE(CPUID_7_1_EDX, 14)



/* Intel-defined sub-features, CPUID level 0x00000007:2 (EDX) */