Commit ae611d17 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: move dpll_funcs to display.funcs 



Move display dpll functions under drm_i915_private display sub-struct.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarArun R Murthy <arun.r.murthy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/5bf7aada2c7f0500c5002fa089fb66a92019a301.1661346845.git.jani.nikula@intel.com
parent 986531bd

drivers/gpu/drm/i915/display/intel_display_core.h

+4 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ struct intel_atomic_state; 
struct intel_cdclk_funcs;

struct intel_crtc;

struct intel_crtc_state;

struct intel_dpll_funcs;

struct intel_initial_plane_config;



struct intel_display_funcs {
@@ -38,6 +39,9 @@ struct intel_display { 


		/* Display CDCLK functions */

		const struct intel_cdclk_funcs *cdclk;



		/* Display pll funcs */

		const struct intel_dpll_funcs *dpll;

	} funcs;

};

drivers/gpu/drm/i915/display/intel_dpll.c

+12 −12
Original line number Diff line number Diff line
@@ -1420,7 +1420,7 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, 
	if (!crtc_state->hw.enable)

		return 0;



	ret = i915->dpll_funcs->crtc_compute_clock(state, crtc);

	ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc);

	if (ret) {

		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",

			    crtc->base.base.id, crtc->base.name);
@@ -1446,10 +1446,10 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, 
	if (!crtc_state->hw.enable)

		return 0;



	if (!i915->dpll_funcs->crtc_get_shared_dpll)

	if (!i915->display.funcs.dpll->crtc_get_shared_dpll)

		return 0;



	ret = i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);

	ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc);

	if (ret) {

		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",

			    crtc->base.base.id, crtc->base.name);
@@ -1463,23 +1463,23 @@ void 
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)

{

	if (IS_DG2(dev_priv))

		dev_priv->dpll_funcs = &dg2_dpll_funcs;

		dev_priv->display.funcs.dpll = &dg2_dpll_funcs;

	else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))

		dev_priv->dpll_funcs = &hsw_dpll_funcs;

		dev_priv->display.funcs.dpll = &hsw_dpll_funcs;

	else if (HAS_PCH_SPLIT(dev_priv))

		dev_priv->dpll_funcs = &ilk_dpll_funcs;

		dev_priv->display.funcs.dpll = &ilk_dpll_funcs;

	else if (IS_CHERRYVIEW(dev_priv))

		dev_priv->dpll_funcs = &chv_dpll_funcs;

		dev_priv->display.funcs.dpll = &chv_dpll_funcs;

	else if (IS_VALLEYVIEW(dev_priv))

		dev_priv->dpll_funcs = &vlv_dpll_funcs;

		dev_priv->display.funcs.dpll = &vlv_dpll_funcs;

	else if (IS_G4X(dev_priv))

		dev_priv->dpll_funcs = &g4x_dpll_funcs;

		dev_priv->display.funcs.dpll = &g4x_dpll_funcs;

	else if (IS_PINEVIEW(dev_priv))

		dev_priv->dpll_funcs = &pnv_dpll_funcs;

		dev_priv->display.funcs.dpll = &pnv_dpll_funcs;

	else if (DISPLAY_VER(dev_priv) != 2)

		dev_priv->dpll_funcs = &i9xx_dpll_funcs;

		dev_priv->display.funcs.dpll = &i9xx_dpll_funcs;

	else

		dev_priv->dpll_funcs = &i8xx_dpll_funcs;

		dev_priv->display.funcs.dpll = &i8xx_dpll_funcs;

}



static bool i9xx_has_pps(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_drv.h

+0 −4
Original line number Diff line number Diff line
@@ -90,7 +90,6 @@ struct intel_color_funcs; 
struct intel_connector;

struct intel_crtc;

struct intel_dp;

struct intel_dpll_funcs;

struct intel_encoder;

struct intel_fbdev;

struct intel_fdi_funcs;
@@ -516,9 +515,6 @@ struct drm_i915_private { 
	/* fdi display functions */

	const struct intel_fdi_funcs *fdi_funcs;



	/* display pll funcs */

	const struct intel_dpll_funcs *dpll_funcs;



	/* Display internal color functions */

	const struct intel_color_funcs *color_funcs;