Commit ae560c43 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Shawn Guo
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arm64: dts: imx8mq-librem5-devkit: Align pin configuration group names with schema 



Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:

    ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent ad5260e0

arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts

+6 −6
Original line number Original line Diff line number Diff line
@@ -735,7 +735,7 @@ 
		>;

		>;

	};

	};





	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {

		fsl,pins = <

		fsl,pins = <

			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d

			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d

			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd

			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
@@ -752,7 +752,7 @@ 
		>;

		>;

	};

	};





	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {

		fsl,pins = <

		fsl,pins = <

			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f

			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f

			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf

			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
@@ -769,13 +769,13 @@ 
		>;

		>;

	};

	};





	pinctrl_usdhc2_pwr: usdhc2grppwr {

	pinctrl_usdhc2_pwr: usdhc2pwrgrp {

		fsl,pins = <

		fsl,pins = <

			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41

			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41

		>;

		>;

	};

	};





	pinctrl_usdhc2_gpio: usdhc2grpgpio {

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {

		fsl,pins = <

		fsl,pins = <

			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20		0x80 /* WIFI_WAKE */

			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20		0x80 /* WIFI_WAKE */

		>;

		>;
@@ -792,7 +792,7 @@ 
		>;

		>;

	};

	};





	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

		fsl,pins = <

		fsl,pins = <

			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x8d

			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x8d

			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcd

			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcd
@@ -803,7 +803,7 @@ 
		>;

		>;

	};

	};





	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {

		fsl,pins = <

		fsl,pins = <

			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f

			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f

			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcf

			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcf