Commit ae4e3b62 authored Mar 20, 2020 by Le Ma Committed by Alex Deucher Jul 01, 2020

drm/amdgpu/mes: add status fence memory definitions



Update for new member query_status_fence_gpu_mc_ptr in MESAPI_SET_HW_RESOURCES.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 4842b9f3

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

+3 −0

Original line number	Original line	Diff line number	Diff line
	@@ -82,6 +82,9 @@ struct amdgpu_mes {
	uint32_t sch_ctx_offs;		uint32_t sch_ctx_offs;
	uint64_t sch_ctx_gpu_addr;		uint64_t sch_ctx_gpu_addr;
	uint64_t *sch_ctx_ptr;		uint64_t *sch_ctx_ptr;
			uint32_t query_status_fence_offs;
			uint64_t query_status_fence_gpu_addr;
			uint64_t *query_status_fence_ptr;

	/* ip specific functions */		/* ip specific functions */
	const struct amdgpu_mes_funcs *funcs;		const struct amdgpu_mes_funcs *funcs;

drivers/gpu/drm/amd/amdgpu/mes_v10_1.c

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -237,6 +237,8 @@ static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes)
	mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;		mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
	mes_set_hw_res_pkt.paging_vmid = 0;		mes_set_hw_res_pkt.paging_vmid = 0;
	mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;		mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
			mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
			mes->query_status_fence_gpu_addr;

	for (i = 0; i < MAX_COMPUTE_PIPES; i++)		for (i = 0; i < MAX_COMPUTE_PIPES; i++)
	mes_set_hw_res_pkt.compute_hqd_mask[i] =		mes_set_hw_res_pkt.compute_hqd_mask[i] =