Commit ae4bffb5 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch 'kvm-arm64/ttl-for-arm64' into HEAD 



Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents f9a026e3 c10bc62a

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -62,7 +62,8 @@ 
#define ARM64_HAS_GENERIC_AUTH			52

#define ARM64_HAS_32BIT_EL1			53

#define ARM64_BTI				54

#define ARM64_HAS_ARMv8_4_TTL			55



#define ARM64_NCAPS				55

#define ARM64_NCAPS				56



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/pgtable-hwdef.h

+2 −0
Original line number Diff line number Diff line
@@ -178,10 +178,12 @@ 
#define PTE_S2_RDONLY		(_AT(pteval_t, 1) << 6)   /* HAP[2:1] */

#define PTE_S2_RDWR		(_AT(pteval_t, 3) << 6)   /* HAP[2:1] */

#define PTE_S2_XN		(_AT(pteval_t, 2) << 53)  /* XN[1:0] */

#define PTE_S2_SW_RESVD		(_AT(pteval_t, 15) << 55) /* Reserved for SW */



#define PMD_S2_RDONLY		(_AT(pmdval_t, 1) << 6)   /* HAP[2:1] */

#define PMD_S2_RDWR		(_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */

#define PMD_S2_XN		(_AT(pmdval_t, 2) << 53)  /* XN[1:0] */

#define PMD_S2_SW_RESVD		(_AT(pmdval_t, 15) << 55) /* Reserved for SW */



#define PUD_S2_RDONLY		(_AT(pudval_t, 1) << 6)   /* HAP[2:1] */

#define PUD_S2_RDWR		(_AT(pudval_t, 3) << 6)   /* HAP[2:1] */

arch/arm64/include/asm/stage2_pgtable.h

+9 −0
Original line number Diff line number Diff line
@@ -256,4 +256,13 @@ stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) 
	return (boundary - 1 < end - 1) ? boundary : end;

}



/*

 * Level values for the ARMv8.4-TTL extension, mapping PUD/PMD/PTE and

 * the architectural page-table level.

 */

#define S2_NO_LEVEL_HINT	0

#define S2_PUD_LEVEL		1

#define S2_PMD_LEVEL		2

#define S2_PTE_LEVEL		3



#endif	/* __ARM64_S2_PGTABLE_H_ */

arch/arm64/include/asm/sysreg.h

+1 −0
Original line number Diff line number Diff line
@@ -746,6 +746,7 @@ 


/* id_aa64mmfr2 */

#define ID_AA64MMFR2_E0PD_SHIFT		60

#define ID_AA64MMFR2_TTL_SHIFT		48

#define ID_AA64MMFR2_FWB_SHIFT		40

#define ID_AA64MMFR2_AT_SHIFT		32

#define ID_AA64MMFR2_LVA_SHIFT		16

arch/arm64/include/asm/tlbflush.h

+45 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 


#ifndef __ASSEMBLY__



#include <linux/bitfield.h>

#include <linux/mm_types.h>

#include <linux/sched.h>

#include <asm/cputype.h>
@@ -59,6 +60,50 @@ 
		__ta;						\

	})



/*

 * Level-based TLBI operations.

 *

 * When ARMv8.4-TTL exists, TLBI operations take an additional hint for

 * the level at which the invalidation must take place. If the level is

 * wrong, no invalidation may take place. In the case where the level

 * cannot be easily determined, a 0 value for the level parameter will

 * perform a non-hinted invalidation.

 *

 * For Stage-2 invalidation, use the level values provided to that effect

 * in asm/stage2_pgtable.h.

 */

#define TLBI_TTL_MASK		GENMASK_ULL(47, 44)

#define TLBI_TTL_TG_4K		1

#define TLBI_TTL_TG_16K		2

#define TLBI_TTL_TG_64K		3



#define __tlbi_level(op, addr, level)					\

	do {								\

		u64 arg = addr;						\

									\

		if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) &&	\

		    level) {						\

			u64 ttl = level & 3;				\

									\

			switch (PAGE_SIZE) {				\

			case SZ_4K:					\

				ttl |= TLBI_TTL_TG_4K << 2;		\

				break;					\

			case SZ_16K:					\

				ttl |= TLBI_TTL_TG_16K << 2;		\

				break;					\

			case SZ_64K:					\

				ttl |= TLBI_TTL_TG_64K << 2;		\

				break;					\

			}						\

									\

			arg &= ~TLBI_TTL_MASK;				\

			arg |= FIELD_PREP(TLBI_TTL_MASK, ttl);		\

		}							\

									\

		__tlbi(op, arg);					\

	} while(0)



/*

 *	TLB Invalidation

 *	================