Commit ae2c341e authored by Geetha sowjanya's avatar Geetha sowjanya Committed by David S. Miller
Browse files

octeontx2-af: cn10k: Set cache lines for NPA batch alloc 



Set NPA batch allocation engine to process 35 cache lines
per turn on CN10k platform.

Signed-off-by: default avatarGeetha sowjanya <gakula@marvell.com>
Signed-off-by: default avatarSunil Goutham <sgoutham@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 87e5ef4b

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+1 −0
Original line number Diff line number Diff line
@@ -594,6 +594,7 @@ struct npa_lf_alloc_rsp { 
	u32 stack_pg_ptrs;  /* No of ptrs per stack page */

	u32 stack_pg_bytes; /* Size of stack page */

	u16 qints; /* NPA_AF_CONST::QINTS */

	u8 cache_lines; /*BATCH ALLOC DMA */

};



/* NPA AQ enqueue msg */

drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c

+11 −0
Original line number Diff line number Diff line
@@ -419,6 +419,10 @@ int rvu_mbox_handler_npa_lf_alloc(struct rvu *rvu, 
	rsp->stack_pg_ptrs = (cfg >> 8) & 0xFF;

	rsp->stack_pg_bytes = cfg & 0xFF;

	rsp->qints = (cfg >> 28) & 0xFFF;

	if (!is_rvu_otx2(rvu)) {

		cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL);

		rsp->cache_lines = (cfg >> 1) & 0x3F;

	}

	return rc;

}
@@ -478,6 +482,13 @@ static int npa_aq_init(struct rvu *rvu, struct rvu_block *block) 
#endif

	rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg);



	/* For CN10K NPA BATCH DMA set 35 cache lines */

	if (!is_rvu_otx2(rvu)) {

		cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL);

		cfg &= ~0x7EULL;

		cfg |= BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1);

		rvu_write64(rvu, block->addr, NPA_AF_BATCH_CTL, cfg);

	}

	/* Result structure can be followed by Aura/Pool context at

	 * RES + 128bytes and a write mask at RES + 256 bytes, depending on

	 * operation type. Alloc sufficient result memory for all operations.

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -156,6 +156,7 @@ 
#define NPA_AF_AQ_DONE_INT_W1S          (0x0688)

#define NPA_AF_AQ_DONE_ENA_W1S          (0x0690)

#define NPA_AF_AQ_DONE_ENA_W1C          (0x0698)

#define NPA_AF_BATCH_CTL		(0x06a0)

#define NPA_AF_LFX_AURAS_CFG(a)         (0x4000 | (a) << 18)

#define NPA_AF_LFX_LOC_AURAS_BASE(a)    (0x4010 | (a) << 18)

#define NPA_AF_LFX_QINTS_CFG(a)         (0x4100 | (a) << 18)