Commit ae1c0d6e authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Gregory CLEMENT
Browse files

arm64: dts: marvell: add missing cache properties 



As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:

  ac5-98dx35xx-rd.dtb: l2-cache: 'cache-unified' is a required property

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
parent ac9a7868

arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ 
		l2: l2-cache {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
			cache-line-size = <64>;

			cache-sets = <512>;

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -82,6 +82,7 @@ 
			cache-line-size = <64>;

			cache-sets = <512>;

			cache-level = <2>;

			cache-unified;

		};



		l2_1: l2-cache1 {
@@ -90,6 +91,7 @@ 
			cache-line-size = <64>;

			cache-sets = <512>;

			cache-level = <2>;

			cache-unified;

		};

	};

};

arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -82,6 +82,7 @@ 
			cache-line-size = <64>;

			cache-sets = <512>;

			cache-level = <2>;

			cache-unified;

		};



		l2_1: l2-cache1 {
@@ -90,6 +91,7 @@ 
			cache-line-size = <64>;

			cache-sets = <512>;

			cache-level = <2>;

			cache-unified;

		};

	};

};