Commit ae07a9a8 authored by Changhuang Liang's avatar Changhuang Liang Committed by Vinod Koul
Browse files

dt-bindings: phy: Add starfive,jh7110-dphy-rx



StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on
a M31 IP. Add a binding for it.

Signed-off-by: default avatarChanghuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230718070803.16660-2-changhuang.liang@starfivetech.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 86fe3e9f
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive SoC JH7110 MIPI D-PHY Rx Controller

maintainers:
  - Jack Zhu <jack.zhu@starfivetech.com>
  - Changhuang Liang <changhuang.liang@starfivetech.com>

description:
  StarFive SoCs contain a MIPI CSI D-PHY based on M31 IP, used to
  transfer CSI camera data.

properties:
  compatible:
    const: starfive,jh7110-dphy-rx

  reg:
    maxItems: 1

  clocks:
    items:
      - description: config clock
      - description: reference clock
      - description: escape mode transmit clock

  clock-names:
    items:
      - const: cfg
      - const: ref
      - const: tx

  resets:
    items:
      - description: DPHY_HW reset
      - description: DPHY_B09_ALWAYS_ON reset

  power-domains:
    maxItems: 1

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - power-domains
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    phy@19820000 {
      compatible = "starfive,jh7110-dphy-rx";
      reg = <0x19820000 0x10000>;
      clocks = <&ispcrg 3>,
               <&ispcrg 4>,
               <&ispcrg 5>;
      clock-names = "cfg", "ref", "tx";
      resets = <&ispcrg 2>,
               <&ispcrg 3>;
      power-domains = <&aon_syscon 1>;
      #phy-cells = <0>;
    };