Commit adfb8165 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx7: use cached values for raster config in clear state 



Use the cached values rather than hardcoding it.

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 93442184

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+2 −23
Original line number Diff line number Diff line
@@ -2551,29 +2551,8 @@ static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) 


	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));

	amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);

	switch (adev->asic_type) {

	case CHIP_BONAIRE:

		amdgpu_ring_write(ring, 0x16000012);

		amdgpu_ring_write(ring, 0x00000000);

		break;

	case CHIP_KAVERI:

		amdgpu_ring_write(ring, 0x00000000); /* XXX */

		amdgpu_ring_write(ring, 0x00000000);

		break;

	case CHIP_KABINI:

	case CHIP_MULLINS:

		amdgpu_ring_write(ring, 0x00000000); /* XXX */

		amdgpu_ring_write(ring, 0x00000000);

		break;

	case CHIP_HAWAII:

		amdgpu_ring_write(ring, 0x3a00161a);

		amdgpu_ring_write(ring, 0x0000002e);

		break;

	default:

		amdgpu_ring_write(ring, 0x00000000);

		amdgpu_ring_write(ring, 0x00000000);

		break;

	}

	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);

	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);



	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);