Commit adf8238e authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

ARM: dts: exynos: move exynos-bus nodes out of soc in Exynos4412 

The soc node is supposed to have only device nodes with MMIO addresses,
as reported by dtc W=1:

  exynos4412.dtsi:407.20-413.5:
    Warning (simple_bus_reg): /soc/bus-acp: missing or empty reg/ranges property

and dtbs_check:

  exynos4412-i9300.dtb: soc: bus-acp:
    {'compatible': ['samsung,exynos-bus'], 'clocks': [[7, 456]], 'clock-names': ['bus'], 'operating-points-v2': [[132]], 'status': ['okay'], 'devfreq': [[117]]} should not be valid under {'type': 'object'}

Move the bus nodes and their OPP tables out of SoC to fix this.
Re-order them alphabetically while moving and put some of the OPP tables
in device nodes (if they are not shared).

Link: https://lore.kernel.org/r/20230125094513.155063-5-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 09dd3739

arch/arm/boot/dts/exynos4412.dtsi

+175 −176
Original line number Diff line number Diff line
@@ -31,6 +31,134 @@ 
		mshc0 = &mshc_0;

	};



	bus_acp: bus-acp {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_DIV_ACP>;

		clock-names = "bus";

		operating-points-v2 = <&bus_acp_opp_table>;

		status = "disabled";



		bus_acp_opp_table: opp-table {

			compatible = "operating-points-v2";



			opp-100000000 {

				opp-hz = /bits/ 64 <100000000>;

			};

			opp-134000000 {

				opp-hz = /bits/ 64 <134000000>;

			};

			opp-160000000 {

				opp-hz = /bits/ 64 <160000000>;

			};

			opp-267000000 {

				opp-hz = /bits/ 64 <267000000>;

			};

		};

	};



	bus_c2c: bus-c2c {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_DIV_C2C>;

		clock-names = "bus";

		operating-points-v2 = <&bus_dmc_opp_table>;

		status = "disabled";

	};



	bus_dmc: bus-dmc {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_DIV_DMC>;

		clock-names = "bus";

		operating-points-v2 = <&bus_dmc_opp_table>;

		samsung,data-clock-ratio = <4>;

		#interconnect-cells = <0>;

		status = "disabled";

	};



	bus_display: bus-display {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_ACLK160>;

		clock-names = "bus";

		operating-points-v2 = <&bus_display_opp_table>;

		interconnects = <&bus_leftbus &bus_dmc>;

		#interconnect-cells = <0>;

		status = "disabled";



		bus_display_opp_table: opp-table {

			compatible = "operating-points-v2";



			opp-160000000 {

				opp-hz = /bits/ 64 <160000000>;

			};

			opp-200000000 {

				opp-hz = /bits/ 64 <200000000>;

			};

		};

	};



	bus_fsys: bus-fsys {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_ACLK133>;

		clock-names = "bus";

		operating-points-v2 = <&bus_fsys_opp_table>;

		status = "disabled";



		bus_fsys_opp_table: opp-table {

			compatible = "operating-points-v2";



			opp-100000000 {

				opp-hz = /bits/ 64 <100000000>;

			};

			opp-134000000 {

				opp-hz = /bits/ 64 <134000000>;

			};

		};

	};



	bus_leftbus: bus-leftbus {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_DIV_GDL>;

		clock-names = "bus";

		operating-points-v2 = <&bus_leftbus_opp_table>;

		interconnects = <&bus_dmc>;

		#interconnect-cells = <0>;

		status = "disabled";

	};



	bus_mfc: bus-mfc {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_SCLK_MFC>;

		clock-names = "bus";

		operating-points-v2 = <&bus_leftbus_opp_table>;

		status = "disabled";

	};



	bus_peri: bus-peri {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_ACLK100>;

		clock-names = "bus";

		operating-points-v2 = <&bus_peri_opp_table>;

		status = "disabled";



		bus_peri_opp_table: opp-table {

			compatible = "operating-points-v2";



			opp-50000000 {

				opp-hz = /bits/ 64 <50000000>;

			};

			opp-100000000 {

				opp-hz = /bits/ 64 <100000000>;

			};

		};

	};



	bus_rightbus: bus-rightbus {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_DIV_GDR>;

		clock-names = "bus";

		operating-points-v2 = <&bus_leftbus_opp_table>;

		status = "disabled";

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -171,6 +299,53 @@ 
		};

	};



	bus_dmc_opp_table: opp-table-1 {

		compatible = "operating-points-v2";



		opp-100000000 {

			opp-hz = /bits/ 64 <100000000>;

			opp-microvolt = <900000>;

		};

		opp-134000000 {

			opp-hz = /bits/ 64 <134000000>;

			opp-microvolt = <900000>;

		};

		opp-160000000 {

			opp-hz = /bits/ 64 <160000000>;

			opp-microvolt = <900000>;

		};

		opp-267000000 {

			opp-hz = /bits/ 64 <267000000>;

			opp-microvolt = <950000>;

		};

		opp-400000000 {

			opp-hz = /bits/ 64 <400000000>;

			opp-microvolt = <1050000>;

			opp-suspend;

		};

	};



	bus_leftbus_opp_table: opp-table-2 {

		compatible = "operating-points-v2";



		opp-100000000 {

			opp-hz = /bits/ 64 <100000000>;

			opp-microvolt = <900000>;

		};

		opp-134000000 {

			opp-hz = /bits/ 64 <134000000>;

			opp-microvolt = <925000>;

		};

		opp-160000000 {

			opp-hz = /bits/ 64 <160000000>;

			opp-microvolt = <950000>;

		};

		opp-200000000 {

			opp-hz = /bits/ 64 <200000000>;

			opp-microvolt = <1000000>;

			opp-suspend;

		};

	};



	soc: soc {
@@ -393,182 +568,6 @@ 
				 <&isp_clock CLK_ISP_FIMC_LITE1>;

			#iommu-cells = <0>;

		};



		bus_dmc: bus-dmc {

			compatible = "samsung,exynos-bus";

			clocks = <&clock CLK_DIV_DMC>;

			clock-names = "bus";

			operating-points-v2 = <&bus_dmc_opp_table>;

			samsung,data-clock-ratio = <4>;

			#interconnect-cells = <0>;

			status = "disabled";

		};



		bus_acp: bus-acp {

			compatible = "samsung,exynos-bus";

			clocks = <&clock CLK_DIV_ACP>;

			clock-names = "bus";

			operating-points-v2 = <&bus_acp_opp_table>;

			status = "disabled";

		};



		bus_c2c: bus-c2c {

			compatible = "samsung,exynos-bus";

			clocks = <&clock CLK_DIV_C2C>;

			clock-names = "bus";

			operating-points-v2 = <&bus_dmc_opp_table>;

			status = "disabled";

		};



		bus_dmc_opp_table: opp-table-1 {

			compatible = "operating-points-v2";



			opp-100000000 {

				opp-hz = /bits/ 64 <100000000>;

				opp-microvolt = <900000>;

			};

			opp-134000000 {

				opp-hz = /bits/ 64 <134000000>;

				opp-microvolt = <900000>;

			};

			opp-160000000 {

				opp-hz = /bits/ 64 <160000000>;

				opp-microvolt = <900000>;

			};

			opp-267000000 {

				opp-hz = /bits/ 64 <267000000>;

				opp-microvolt = <950000>;

			};

			opp-400000000 {

				opp-hz = /bits/ 64 <400000000>;

				opp-microvolt = <1050000>;

				opp-suspend;

			};

		};



		bus_acp_opp_table: opp-table-2 {

			compatible = "operating-points-v2";



			opp-100000000 {

				opp-hz = /bits/ 64 <100000000>;

			};

			opp-134000000 {

				opp-hz = /bits/ 64 <134000000>;

			};

			opp-160000000 {

				opp-hz = /bits/ 64 <160000000>;

			};

			opp-267000000 {

				opp-hz = /bits/ 64 <267000000>;

			};

		};



		bus_leftbus: bus-leftbus {

			compatible = "samsung,exynos-bus";

			clocks = <&clock CLK_DIV_GDL>;

			clock-names = "bus";

			operating-points-v2 = <&bus_leftbus_opp_table>;

			interconnects = <&bus_dmc>;

			#interconnect-cells = <0>;

			status = "disabled";

		};



		bus_rightbus: bus-rightbus {

			compatible = "samsung,exynos-bus";

			clocks = <&clock CLK_DIV_GDR>;

			clock-names = "bus";

			operating-points-v2 = <&bus_leftbus_opp_table>;

			status = "disabled";

		};



		bus_display: bus-display {

			compatible = "samsung,exynos-bus";

			clocks = <&clock CLK_ACLK160>;

			clock-names = "bus";

			operating-points-v2 = <&bus_display_opp_table>;

			interconnects = <&bus_leftbus &bus_dmc>;

			#interconnect-cells = <0>;

			status = "disabled";

		};



		bus_fsys: bus-fsys {

			compatible = "samsung,exynos-bus";

			clocks = <&clock CLK_ACLK133>;

			clock-names = "bus";

			operating-points-v2 = <&bus_fsys_opp_table>;

			status = "disabled";

		};



		bus_peri: bus-peri {

			compatible = "samsung,exynos-bus";

			clocks = <&clock CLK_ACLK100>;

			clock-names = "bus";

			operating-points-v2 = <&bus_peri_opp_table>;

			status = "disabled";

		};



		bus_mfc: bus-mfc {

			compatible = "samsung,exynos-bus";

			clocks = <&clock CLK_SCLK_MFC>;

			clock-names = "bus";

			operating-points-v2 = <&bus_leftbus_opp_table>;

			status = "disabled";

		};



		bus_leftbus_opp_table: opp-table-3 {

			compatible = "operating-points-v2";



			opp-100000000 {

				opp-hz = /bits/ 64 <100000000>;

				opp-microvolt = <900000>;

			};

			opp-134000000 {

				opp-hz = /bits/ 64 <134000000>;

				opp-microvolt = <925000>;

			};

			opp-160000000 {

				opp-hz = /bits/ 64 <160000000>;

				opp-microvolt = <950000>;

			};

			opp-200000000 {

				opp-hz = /bits/ 64 <200000000>;

				opp-microvolt = <1000000>;

				opp-suspend;

			};

		};



		bus_display_opp_table: opp-table-4 {

			compatible = "operating-points-v2";



			opp-160000000 {

				opp-hz = /bits/ 64 <160000000>;

			};

			opp-200000000 {

				opp-hz = /bits/ 64 <200000000>;

			};

		};



		bus_fsys_opp_table: opp-table-5 {

			compatible = "operating-points-v2";



			opp-100000000 {

				opp-hz = /bits/ 64 <100000000>;

			};

			opp-134000000 {

				opp-hz = /bits/ 64 <134000000>;

			};

		};



		bus_peri_opp_table: opp-table-6 {

			compatible = "operating-points-v2";



			opp-50000000 {

				opp-hz = /bits/ 64 <50000000>;

			};

			opp-100000000 {

				opp-hz = /bits/ 64 <100000000>;

			};

		};

	};

};