Commit adc27288 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue 



Tony Nguyen says:

====================
100GbE Intel Wired LAN Driver Updates 2022-02-09

This series contains updates to ice driver only.

Brett adds support for QinQ. This begins with code refactoring and
re-organization of VLAN configuration functions to allow for
introduction of VSI VLAN ops to enable setting and calling of
respective operations based on device support of single or double
VLANs. Implementations are added for outer VLAN support.

To support QinQ, the device must be set to double VLAN mode (DVM).
In order for this to occur, the DDP package and NVM must also support
DVM. Functions to determine compatibility and properly configure the
device are added as well as setting the proper bits to advertise and
utilize the proper offloads. Support for VIRTCHNL_VF_OFFLOAD_VLAN_V2
is also included to allow for VF to negotiate and utilize this
functionality.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 45230829 f1da5a08

drivers/net/ethernet/intel/ice/Makefile

+10 −2
Original line number Diff line number Diff line
@@ -18,8 +18,12 @@ ice-y := ice_main.o \ 
	 ice_txrx_lib.o	\

	 ice_txrx.o	\

	 ice_fltr.o	\

	 ice_pf_vsi_vlan_ops.o \

	 ice_vsi_vlan_ops.o \

	 ice_vsi_vlan_lib.o \

	 ice_fdir.o	\

	 ice_ethtool_fdir.o \

	 ice_vlan_mode.o \

	 ice_flex_pipe.o \

	 ice_flow.o	\

	 ice_idc.o	\
@@ -29,8 +33,12 @@ ice-y := ice_main.o \ 
	 ice_ethtool.o  \

	 ice_repr.o	\

	 ice_tc_lib.o

ice-$(CONFIG_PCI_IOV) += ice_virtchnl_allowlist.o

ice-$(CONFIG_PCI_IOV) += ice_virtchnl_pf.o ice_sriov.o ice_virtchnl_fdir.o

ice-$(CONFIG_PCI_IOV) +=	\

	ice_virtchnl_allowlist.o \

	ice_virtchnl_fdir.o	\

	ice_sriov.o		\

	ice_vf_vsi_vlan_ops.o	\

	ice_virtchnl_pf.o

ice-$(CONFIG_PTP_1588_CLOCK) += ice_ptp.o ice_ptp_hw.o

ice-$(CONFIG_DCB) += ice_dcb.o ice_dcb_nl.o ice_dcb_lib.o

ice-$(CONFIG_RFS_ACCEL) += ice_arfs.o

drivers/net/ethernet/intel/ice/ice.h

+4 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ 
#include "ice_repr.h"

#include "ice_eswitch.h"

#include "ice_lag.h"

#include "ice_vsi_vlan_ops.h"



#define ICE_BAR0		0

#define ICE_REQ_DESC_MULTIPLE	32
@@ -368,6 +369,8 @@ struct ice_vsi { 
	u8 irqs_ready:1;

	u8 current_isup:1;		 /* Sync 'link up' logging */

	u8 stat_offsets_loaded:1;

	struct ice_vsi_vlan_ops inner_vlan_ops;

	struct ice_vsi_vlan_ops outer_vlan_ops;

	u16 num_vlan;



	/* queue information */
@@ -482,6 +485,7 @@ enum ice_pf_flags { 
	ICE_FLAG_LEGACY_RX,

	ICE_FLAG_VF_TRUE_PROMISC_ENA,

	ICE_FLAG_MDD_AUTO_RESET_VF,

	ICE_FLAG_VF_VLAN_PRUNING,

	ICE_FLAG_LINK_LENIENT_MODE_ENA,

	ICE_PF_FLAGS_NBITS		/* must be last */

};

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

+161 −94
Original line number Diff line number Diff line
@@ -226,6 +226,15 @@ struct ice_aqc_get_sw_cfg_resp_elem { 
#define ICE_AQC_GET_SW_CONF_RESP_IS_VF		BIT(15)

};



/* Set Port parameters, (direct, 0x0203) */

struct ice_aqc_set_port_params {

	__le16 cmd_flags;

#define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA	BIT(2)

	__le16 bad_frame_vsi;

	__le16 swid;

	u8 reserved[10];

};



/* These resource type defines are used for all switch resource

 * commands where a resource type is required, such as:

 * Get Resource Allocation command (indirect 0x0204)
@@ -283,6 +292,40 @@ struct ice_aqc_alloc_free_res_elem { 
	struct ice_aqc_res_elem elem[];

};



/* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */

struct ice_aqc_set_vlan_mode {

	u8 reserved;

	u8 l2tag_prio_tagging;

#define ICE_AQ_VLAN_PRIO_TAG_S			0

#define ICE_AQ_VLAN_PRIO_TAG_M			(0x7 << ICE_AQ_VLAN_PRIO_TAG_S)

#define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED	0x0

#define ICE_AQ_VLAN_PRIO_TAG_STAG		0x1

#define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG		0x2

#define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN		0x3

#define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG		0x4

#define ICE_AQ_VLAN_PRIO_TAG_MAX		0x4

#define ICE_AQ_VLAN_PRIO_TAG_ERROR		0x7

	u8 l2tag_reserved[64];

	u8 rdma_packet;

#define ICE_AQ_VLAN_RDMA_TAG_S			0

#define ICE_AQ_VLAN_RDMA_TAG_M			(0x3F << ICE_AQ_VLAN_RDMA_TAG_S)

#define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING	0x10

#define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING	0x1A

	u8 rdma_reserved[2];

	u8 mng_vlan_prot_id;

#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER	0x10

#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER	0x11

	u8 prot_id_reserved[30];

};



/* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */

struct ice_aqc_get_vlan_mode {

	u8 vlan_mode;

#define ICE_AQ_VLAN_MODE_DVM_ENA	BIT(0)

	u8 l2tag_prio_tagging;

	u8 reserved[98];

};



/* Add VSI (indirect 0x0210)

 * Update VSI (indirect 0x0211)

 * Get VSI (indirect 0x0212)
@@ -343,8 +386,7 @@ struct ice_aqc_vsi_props { 
#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE		BIT(7)

	u8 sw_flags2;

#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S	0

#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M	\

				(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)

#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M	(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)

#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA	BIT(0)

#define ICE_AQ_VSI_SW_FLAG_LAN_ENA		BIT(4)

	u8 veb_stat_id;
@@ -360,22 +402,22 @@ struct ice_aqc_vsi_props { 
#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA	BIT(0)

	u8 sec_reserved;

	/* VLAN section */

	__le16 pvid; /* VLANS include priority bits */

	u8 pvlan_reserved[2];

	u8 vlan_flags;

#define ICE_AQ_VSI_VLAN_MODE_S	0

#define ICE_AQ_VSI_VLAN_MODE_M	(0x3 << ICE_AQ_VSI_VLAN_MODE_S)

#define ICE_AQ_VSI_VLAN_MODE_UNTAGGED	0x1

#define ICE_AQ_VSI_VLAN_MODE_TAGGED	0x2

#define ICE_AQ_VSI_VLAN_MODE_ALL	0x3

#define ICE_AQ_VSI_PVLAN_INSERT_PVID	BIT(2)

#define ICE_AQ_VSI_VLAN_EMOD_S		3

#define ICE_AQ_VSI_VLAN_EMOD_M		(0x3 << ICE_AQ_VSI_VLAN_EMOD_S)

#define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH	(0x0 << ICE_AQ_VSI_VLAN_EMOD_S)

#define ICE_AQ_VSI_VLAN_EMOD_STR_UP	(0x1 << ICE_AQ_VSI_VLAN_EMOD_S)

#define ICE_AQ_VSI_VLAN_EMOD_STR	(0x2 << ICE_AQ_VSI_VLAN_EMOD_S)

#define ICE_AQ_VSI_VLAN_EMOD_NOTHING	(0x3 << ICE_AQ_VSI_VLAN_EMOD_S)

	u8 pvlan_reserved2[3];

	__le16 port_based_inner_vlan; /* VLANS include priority bits */

	u8 inner_vlan_reserved[2];

	u8 inner_vlan_flags;

#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S		0

#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M		(0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)

#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED	0x1

#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED	0x2

#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL	0x3

#define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID	BIT(2)

#define ICE_AQ_VSI_INNER_VLAN_EMODE_S		3

#define ICE_AQ_VSI_INNER_VLAN_EMODE_M		(0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)

#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH	(0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)

#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP	(0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)

#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR		(0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)

#define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING	(0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)

	u8 inner_vlan_reserved2[3];

	/* ingress egress up sections */

	__le32 ingress_table; /* bitmap, 3 bits per up */

#define ICE_AQ_VSI_UP_TABLE_UP0_S		0
@@ -396,22 +438,28 @@ struct ice_aqc_vsi_props { 
#define ICE_AQ_VSI_UP_TABLE_UP7_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)

	__le32 egress_table;   /* same defines as for ingress table */

	/* outer tags section */

	__le16 outer_tag;

	u8 outer_tag_flags;

#define ICE_AQ_VSI_OUTER_TAG_MODE_S	0

#define ICE_AQ_VSI_OUTER_TAG_MODE_M	(0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)

#define ICE_AQ_VSI_OUTER_TAG_NOTHING	0x0

#define ICE_AQ_VSI_OUTER_TAG_REMOVE	0x1

#define ICE_AQ_VSI_OUTER_TAG_COPY	0x2

	__le16 port_based_outer_vlan;

	u8 outer_vlan_flags;

#define ICE_AQ_VSI_OUTER_VLAN_EMODE_S		0

#define ICE_AQ_VSI_OUTER_VLAN_EMODE_M		(0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)

#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH	0x0

#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP	0x1

#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW	0x2

#define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING	0x3

#define ICE_AQ_VSI_OUTER_TAG_TYPE_S		2

#define ICE_AQ_VSI_OUTER_TAG_TYPE_M		(0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)

#define ICE_AQ_VSI_OUTER_TAG_NONE		0x0

#define ICE_AQ_VSI_OUTER_TAG_STAG		0x1

#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100		0x2

#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100		0x3

#define ICE_AQ_VSI_OUTER_TAG_INSERT	BIT(4)

#define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)

	u8 outer_tag_reserved;

#define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT		BIT(4)

#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S			5

#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M			(0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)

#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED	0x1

#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED	0x2

#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL		0x3

#define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC		BIT(7)

	u8 outer_vlan_reserved;

	/* queue mapping section */

	__le16 mapping_flags;

#define ICE_AQ_VSI_Q_MAP_CONTIG			0x0
@@ -489,9 +537,13 @@ struct ice_aqc_add_get_recipe { 


struct ice_aqc_recipe_content {

	u8 rid;

#define ICE_AQ_RECIPE_ID_S		0

#define ICE_AQ_RECIPE_ID_M		(0x3F << ICE_AQ_RECIPE_ID_S)

#define ICE_AQ_RECIPE_ID_IS_ROOT	BIT(7)

#define ICE_AQ_SW_ID_LKUP_IDX		0

	u8 lkup_indx[5];

#define ICE_AQ_RECIPE_LKUP_DATA_S	0

#define ICE_AQ_RECIPE_LKUP_DATA_M	(0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)

#define ICE_AQ_RECIPE_LKUP_IGNORE	BIT(7)

#define ICE_AQ_SW_ID_LKUP_MASK		0x00FF

	__le16 mask[5];
@@ -502,15 +554,25 @@ struct ice_aqc_recipe_content { 
	u8 rsvd0[3];

	u8 act_ctrl_join_priority;

	u8 act_ctrl_fwd_priority;

#define ICE_AQ_RECIPE_FWD_PRIORITY_S	0

#define ICE_AQ_RECIPE_FWD_PRIORITY_M	(0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)

	u8 act_ctrl;

#define ICE_AQ_RECIPE_ACT_NEED_PASS_L2	BIT(0)

#define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2	BIT(1)

#define ICE_AQ_RECIPE_ACT_INV_ACT	BIT(2)

#define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S	4

#define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M	(0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)

	u8 rsvd1;

	__le32 dflt_act;

#define ICE_AQ_RECIPE_DFLT_ACT_S	0

#define ICE_AQ_RECIPE_DFLT_ACT_M	(0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)

#define ICE_AQ_RECIPE_DFLT_ACT_VALID	BIT(31)

};



struct ice_aqc_recipe_data_elem {

	u8 recipe_indx;

	u8 resp_bits;

#define ICE_AQ_RECIPE_WAS_UPDATED	BIT(0)

	u8 rsvd0[2];

	u8 recipe_bitmap[8];

	u8 rsvd1[4];
@@ -1883,7 +1945,7 @@ struct ice_aqc_get_clear_fw_log { 
};



/* Download Package (indirect 0x0C40) */

/* Also used for Update Package (indirect 0x0C42) */

/* Also used for Update Package (indirect 0x0C41 and 0x0C42) */

struct ice_aqc_download_pkg {

	u8 flags;

#define ICE_AQC_DOWNLOAD_PKG_LAST_BUF	0x01
@@ -2009,6 +2071,7 @@ struct ice_aq_desc { 
		struct ice_aqc_sff_eeprom read_write_sff_param;

		struct ice_aqc_set_port_id_led set_port_id_led;

		struct ice_aqc_get_sw_cfg get_sw_conf;

		struct ice_aqc_set_port_params set_port_params;

		struct ice_aqc_sw_rules sw_rules;

		struct ice_aqc_add_get_recipe add_get_recipe;

		struct ice_aqc_recipe_to_profile recipe_to_profile;
@@ -2110,10 +2173,13 @@ enum ice_adminq_opc { 


	/* internal switch commands */

	ice_aqc_opc_get_sw_cfg				= 0x0200,

	ice_aqc_opc_set_port_params			= 0x0203,



	/* Alloc/Free/Get Resources */

	ice_aqc_opc_alloc_res				= 0x0208,

	ice_aqc_opc_free_res				= 0x0209,

	ice_aqc_opc_set_vlan_mode_parameters		= 0x020C,

	ice_aqc_opc_get_vlan_mode_parameters		= 0x020D,



	/* VSI commands */

	ice_aqc_opc_add_vsi				= 0x0210,
@@ -2204,6 +2270,7 @@ enum ice_adminq_opc { 


	/* package commands */

	ice_aqc_opc_download_pkg			= 0x0C40,

	ice_aqc_opc_upload_section			= 0x0C41,

	ice_aqc_opc_update_pkg				= 0x0C42,

	ice_aqc_opc_get_pkg_info_list			= 0x0C43,

drivers/net/ethernet/intel/ice/ice_base.c

+17 −2
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
#include "ice_base.h"

#include "ice_lib.h"

#include "ice_dcb_lib.h"

#include "ice_virtchnl_pf.h"



static bool ice_alloc_rx_buf_zc(struct ice_rx_ring *rx_ring)

{
@@ -418,7 +419,21 @@ static int ice_setup_rx_ctx(struct ice_rx_ring *ring) 
	 */

	rlan_ctx.crcstrip = 1;



	/* L2TSEL flag defines the reported L2 Tags in the receive descriptor */

	/* L2TSEL flag defines the reported L2 Tags in the receive descriptor

	 * and it needs to remain 1 for non-DVM capable configurations to not

	 * break backward compatibility for VF drivers. Setting this field to 0

	 * will cause the single/outer VLAN tag to be stripped to the L2TAG2_2ND

	 * field in the Rx descriptor. Setting it to 1 allows the VLAN tag to

	 * be stripped in L2TAG1 of the Rx descriptor, which is where VFs will

	 * check for the tag

	 */

	if (ice_is_dvm_ena(hw))

		if (vsi->type == ICE_VSI_VF &&

		    ice_vf_is_port_vlan_ena(&vsi->back->vf[vsi->vf_id]))

			rlan_ctx.l2tsel = 1;

		else

			rlan_ctx.l2tsel = 0;

	else

		rlan_ctx.l2tsel = 1;



	rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT;

drivers/net/ethernet/intel/ice/ice_common.c

+44 −5
Original line number Diff line number Diff line
@@ -1518,16 +1518,27 @@ ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 


	/* When a package download is in process (i.e. when the firmware's

	 * Global Configuration Lock resource is held), only the Download

	 * Package, Get Version, Get Package Info List and Release Resource

	 * (with resource ID set to Global Config Lock) AdminQ commands are

	 * allowed; all others must block until the package download completes

	 * and the Global Config Lock is released.  See also

	 * ice_acquire_global_cfg_lock().

	 * Package, Get Version, Get Package Info List, Upload Section,

	 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters,

	 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get

	 * Recipes to Profile Association, and Release Resource (with resource

	 * ID set to Global Config Lock) AdminQ commands are allowed; all others

	 * must block until the package download completes and the Global Config

	 * Lock is released.  See also ice_acquire_global_cfg_lock().

	 */

	switch (le16_to_cpu(desc->opcode)) {

	case ice_aqc_opc_download_pkg:

	case ice_aqc_opc_get_pkg_info_list:

	case ice_aqc_opc_get_ver:

	case ice_aqc_opc_upload_section:

	case ice_aqc_opc_update_pkg:

	case ice_aqc_opc_set_port_params:

	case ice_aqc_opc_get_vlan_mode_parameters:

	case ice_aqc_opc_set_vlan_mode_parameters:

	case ice_aqc_opc_add_recipe:

	case ice_aqc_opc_recipe_to_profile:

	case ice_aqc_opc_get_recipe:

	case ice_aqc_opc_get_recipe_to_profile:

		break;

	case ice_aqc_opc_release_res:

		if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK)
@@ -2736,6 +2747,34 @@ void ice_clear_pxe_mode(struct ice_hw *hw) 
		ice_aq_clear_pxe_mode(hw);

}



/**

 * ice_aq_set_port_params - set physical port parameters.

 * @pi: pointer to the port info struct

 * @double_vlan: if set double VLAN is enabled

 * @cd: pointer to command details structure or NULL

 *

 * Set Physical port parameters (0x0203)

 */

int

ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan,

		       struct ice_sq_cd *cd)



{

	struct ice_aqc_set_port_params *cmd;

	struct ice_hw *hw = pi->hw;

	struct ice_aq_desc desc;

	u16 cmd_flags = 0;



	cmd = &desc.params.set_port_params;



	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params);

	if (double_vlan)

		cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA;

	cmd->cmd_flags = cpu_to_le16(cmd_flags);



	return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);

}



/**

 * ice_get_link_speed_based_on_phy_type - returns link speed

 * @phy_type_low: lower part of phy_type