Commit adb12f06 authored by Bjorn Andersson's avatar Bjorn Andersson
Browse files

Merge branch '1662005846-4838-1-git-send-email-quic_c_skakit@quicinc.com' into clk-for-6.1

parents 6956c18f 1c3f9df7

Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml

+2 −4
Original line number Diff line number Diff line
@@ -36,13 +36,11 @@ properties: 
    items:

      - description: LPASS qdsp6ss register

      - description: LPASS top-cc register

      - description: LPASS cc register



  reg-names:

    items:

      - const: qdsp6ss

      - const: top_cc

      - const: cc



required:

  - compatible
@@ -59,8 +57,8 @@ examples: 
    #include <dt-bindings/clock/qcom,lpass-sc7280.h>

    clock-controller@3000000 {

      compatible = "qcom,sc7280-lpasscc";

      reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>;

      reg-names = "qdsp6ss", "top_cc", "cc";

      reg = <0x03000000 0x40>, <0x03c04000 0x4>;

      reg-names = "qdsp6ss", "top_cc";

      clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;

      clock-names = "iface";

      #clock-cells = <1>;

Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml

+23 −3
Original line number Diff line number Diff line
@@ -22,6 +22,8 @@ properties: 


  clock-names: true



  reg: true



  compatible:

    enum:

      - qcom,sc7280-lpassaoncc
@@ -38,8 +40,14 @@ properties: 
  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1

  '#reset-cells':

    const: 1



  qcom,adsp-pil-mode:

    description:

      Indicates if the LPASS would be brought out of reset using

      peripheral loader.

    type: boolean



required:

  - compatible
@@ -69,6 +77,11 @@ allOf: 
          items:

            - const: bi_tcxo

            - const: lpass_aon_cc_main_rcg_clk_src



        reg:

          items:

            - description: lpass core cc register

            - description: lpass audio csr register

  - if:

      properties:

        compatible:
@@ -90,6 +103,8 @@ allOf: 
            - const: bi_tcxo_ao

            - const: iface



        reg:

          maxItems: 1

  - if:

      properties:

        compatible:
@@ -108,6 +123,8 @@ allOf: 
          items:

            - const: bi_tcxo



        reg:

          maxItems: 1

examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>
@@ -116,13 +133,15 @@ examples: 
    #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>

    lpass_audiocc: clock-controller@3300000 {

      compatible = "qcom,sc7280-lpassaudiocc";

      reg = <0x3300000 0x30000>;

      reg = <0x3300000 0x30000>,

            <0x32a9000 0x1000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;

      clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";

      power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;

      #clock-cells = <1>;

      #power-domain-cells = <1>;

      #reset-cells = <1>;

    };



  - |
@@ -165,6 +184,7 @@ examples: 
      clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,

               <&lpasscore LPASS_CORE_CC_CORE_CLK>;

      clock-names = "bi_tcxo", "bi_tcxo_ao","iface";

      qcom,adsp-pil-mode;

      #clock-cells = <1>;

      #power-domain-cells = <1>;

    };

include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h

+5 −0
Original line number Diff line number Diff line
@@ -24,6 +24,11 @@ 
#define LPASS_AUDIO_CC_RX_MCLK_CLK			14

#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC			15



/* LPASS AUDIO CC CSR */

#define LPASS_AUDIO_SWR_RX_CGCR				0

#define LPASS_AUDIO_SWR_TX_CGCR				1

#define LPASS_AUDIO_SWR_WSA_CGCR			2



/* LPASS_AON_CC clocks */

#define LPASS_AON_CC_PLL				0

#define LPASS_AON_CC_PLL_OUT_EVEN			1

include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h

+2 −0
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ 
#define LPASS_CORE_CC_LPM_CORE_CLK			9

#define LPASS_CORE_CC_LPM_MEM0_CORE_CLK			10

#define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK		11

#define LPASS_CORE_CC_EXT_MCLK0_CLK			12

#define LPASS_CORE_CC_EXT_MCLK0_CLK_SRC			13



/* LPASS_CORE_CC power domains */

#define LPASS_CORE_CC_LPASS_CORE_HM_GDSC		0