Commit ad9592c0 authored by Amit Cohen's avatar Amit Cohen Committed by David S. Miller
Browse files

mlxsw: reg: Add egress FID field to RITR register 



RITR configures the router interface table. As preparation for unified
bridge model, add egress FID field to RITR.

After routing, a packet has to perform a layer-2 lookup using the
destination MAC it got from the routing and a FID.
In the new model, the egress FID is configured by RITR for both sub-port
and FID RIFs.

Add 'efid' field to sub-port router interface and update FID router
interface related comment.

Signed-off-by: default avatarAmit Cohen <amcohen@nvidia.com>
Reviewed-by: default avatarPetr Machata <petrm@nvidia.com>
Signed-off-by: default avatarIdo Schimmel <idosch@nvidia.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 27f0b6ce

drivers/net/ethernet/mellanox/mlxsw/reg.h

+14 −2
Original line number Diff line number Diff line
@@ -6885,8 +6885,10 @@ MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 
/* FID Interface */



/* reg_ritr_fid_if_fid

 * Filtering ID. Used to connect a bridge to the router. Only FIDs from

 * the vFID range are supported.

 * Filtering ID. Used to connect a bridge to the router.

 * When legacy bridge model is used, only FIDs from the vFID range are

 * supported. When unified bridge model is used, this is the egress FID for

 * router to bridge.

 * Access: RW

 */

MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
@@ -6917,6 +6919,16 @@ MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 
 */

MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);



/* reg_ritr_sp_if_efid

 * Egress filtering ID.

 * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or

 * the VID.

 * Access: RW

 *

 * Note: Reserved when legacy bridge model is used.

 */

MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16);



/* reg_ritr_sp_if_vid

 * VLAN ID.

 * Access: RW