Commit ad6b47cd authored by Samuel Holland's avatar Samuel Holland Committed by Marc Zyngier
Browse files

dt-bindings: irq: sun6i-r: Split the binding from sun7i-nmi 



The R_INTC in the A31 and newer sun8i/sun50i SoCs has additional
functionality compared to the sun7i/sun9i NMI controller. Among other
things, it multiplexes access to up to 128 interrupts corresponding to
(and in parallel to) the first 128 GIC SPIs. This means the NMI is no
longer the lowest-numbered hwirq at this irqchip, since it is SPI 32 or
96 (depending on SoC). hwirq 0 now corresponds to SPI 0, usually UART0.

To allow access to all multiplexed IRQs, the R_INTC requires a new
binding where the interrupt number matches the GIC interrupt number.
Otherwise, interrupts with hwirq numbers below the NMI would not be
representable in the device tree.

For simplicity, copy the three-cell GIC binding; this disambiguates
interrupt 0 in the old binding (the NMI) from interrupt 0 in the new
binding (SPI 0) by the number of cells.

Because the H6 R_INTC has a different mapping from multiplexed IRQs to
top-level register bits, it is no longer compatible with the A31 R_INTC.

Acked-by: default avatarMaxime Ripard <mripard@kernel.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210118055040.21910-2-samuel@sholland.org
parent d4034114

Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Allwinner A31 NMI/Wakeup Interrupt Controller Device Tree Bindings



maintainers:

  - Chen-Yu Tsai <wens@csie.org>

  - Maxime Ripard <mripard@kernel.org>



allOf:

  - $ref: /schemas/interrupt-controller.yaml#



properties:

  "#interrupt-cells":

    const: 3

    description:

      The first cell is GIC_SPI (0), the second cell is the IRQ number, and

      the third cell is the trigger type as defined in interrupt.txt in this

      directory.



  compatible:

    oneOf:

      - const: allwinner,sun6i-a31-r-intc

      - items:

          - enum:

              - allwinner,sun8i-a83t-r-intc

              - allwinner,sun50i-a64-r-intc

          - const: allwinner,sun6i-a31-r-intc

      - const: allwinner,sun50i-h6-r-intc



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1

    description:

      The GIC interrupt labeled as "External NMI".



  interrupt-controller: true



required:

  - "#interrupt-cells"

  - compatible

  - reg

  - interrupts

  - interrupt-controller



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    r_intc: interrupt-controller@1f00c00 {

            compatible = "allwinner,sun50i-a64-r-intc",

                         "allwinner,sun6i-a31-r-intc";

            interrupt-controller;

            #interrupt-cells = <3>;

            reg = <0x01f00c00 0x400>;

            interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

    };



...

Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml

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@@ -22,23 +22,13 @@ properties: 


  compatible:

    oneOf:

      - const: allwinner,sun6i-a31-r-intc

      - const: allwinner,sun6i-a31-sc-nmi

        deprecated: true

      - const: allwinner,sun7i-a20-sc-nmi

      - items:

          - const: allwinner,sun8i-a83t-r-intc

          - const: allwinner,sun6i-a31-r-intc

      - const: allwinner,sun9i-a80-nmi

      - items:

          - const: allwinner,sun50i-a64-r-intc

          - const: allwinner,sun6i-a31-r-intc

      - items:

          - const: allwinner,sun50i-a100-nmi

          - const: allwinner,sun9i-a80-nmi

      - items:

          - const: allwinner,sun50i-h6-r-intc

          - const: allwinner,sun6i-a31-r-intc



  reg:

    maxItems: 1