Commit ad69b73a authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark
Browse files

drm/msm/dsi/phy: fix clock names in 28nm_8960 phy 



The commit 9f91f22a ("drm/msm/dsi: remove duplicate fields from
dsi_pll_Nnm instances") mistakenly changed registered clock names. While
the platform is in progress of migration to using clock properties in
the dts rather than the global clock names, we should provide backwards
compatibility. Thus restore registerd global clock names.

Fixes: 9f91f22a ("drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances")
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
Link: https://lore.kernel.org/r/20210921162245.1858118-1-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 3431c17b

drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c

+2 −2
Original line number Diff line number Diff line
@@ -428,7 +428,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov 
	bytediv->reg = pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9;



	snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->phy->id);

	snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id);

	snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id + 1);



	bytediv_init.name = clk_name;

	bytediv_init.ops = &clk_bytediv_ops;
@@ -442,7 +442,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov 
		return ret;

	provided_clocks[DSI_BYTE_PLL_CLK] = &bytediv->hw;



	snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id);

	snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id + 1);

	/* DIV3 */

	hw = devm_clk_hw_register_divider(dev, clk_name,

				parent_name, 0, pll_28nm->phy->pll_base +