Unverified Commit ad635e72 authored by Sunil V L's avatar Sunil V L Committed by Palmer Dabbelt
Browse files

riscv: cpu: Add 64bit hartid support on RV64 



The hartid can be a 64bit value on RV64 platforms.

Add support for 64bit hartid in riscv_of_processor_hartid() and
update its callers.

Signed-off-by: default avatarSunil V L <sunilvl@ventanamicro.com>
Reviewed-by: default avatarAtish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20220527051743.2829940-5-sunilvl@ventanamicro.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 62750eae

arch/riscv/include/asm/processor.h

+2 −2
Original line number Diff line number Diff line
@@ -79,8 +79,8 @@ static inline void wait_for_interrupt(void) 
}



struct device_node;

int riscv_of_processor_hartid(struct device_node *node);

int riscv_of_parent_hartid(struct device_node *node);

int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);

int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);



extern void riscv_fill_hwcap(void);

extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);

arch/riscv/kernel/cpu.c

+15 −11
Original line number Diff line number Diff line
@@ -14,37 +14,36 @@ 
 * Returns the hart ID of the given device tree node, or -ENODEV if the node

 * isn't an enabled and valid RISC-V hart node.

 */

int riscv_of_processor_hartid(struct device_node *node)

int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)

{

	const char *isa;

	u32 hart;



	if (!of_device_is_compatible(node, "riscv")) {

		pr_warn("Found incompatible CPU\n");

		return -ENODEV;

	}



	hart = of_get_cpu_hwid(node, 0);

	if (hart == ~0U) {

	*hart = (unsigned long) of_get_cpu_hwid(node, 0);

	if (*hart == ~0UL) {

		pr_warn("Found CPU without hart ID\n");

		return -ENODEV;

	}



	if (!of_device_is_available(node)) {

		pr_info("CPU with hartid=%d is not available\n", hart);

		pr_info("CPU with hartid=%lu is not available\n", *hart);

		return -ENODEV;

	}



	if (of_property_read_string(node, "riscv,isa", &isa)) {

		pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart);

		pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);

		return -ENODEV;

	}

	if (isa[0] != 'r' || isa[1] != 'v') {

		pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa);

		pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);

		return -ENODEV;

	}



	return hart;

	return 0;

}



/*
@@ -53,11 +52,16 @@ int riscv_of_processor_hartid(struct device_node *node) 
 * To achieve this, we walk up the DT tree until we find an active

 * RISC-V core (HART) node and extract the cpuid from it.

 */

int riscv_of_parent_hartid(struct device_node *node)

int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)

{

	int rc;



	for (; node; node = node->parent) {

		if (of_device_is_compatible(node, "riscv"))

			return riscv_of_processor_hartid(node);

		if (of_device_is_compatible(node, "riscv")) {

			rc = riscv_of_processor_hartid(node, hartid);

			if (!rc)

				return 0;

		}

	}



	return -1;

arch/riscv/kernel/cpufeature.c

+4 −2
Original line number Diff line number Diff line
@@ -73,8 +73,9 @@ void __init riscv_fill_hwcap(void) 
	struct device_node *node;

	const char *isa;

	char print_str[NUM_ALPHA_EXTS + 1];

	int i, j;

	int i, j, rc;

	static unsigned long isa2hwcap[256] = {0};

	unsigned long hartid;



	isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;

	isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M;
@@ -92,7 +93,8 @@ void __init riscv_fill_hwcap(void) 
		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);

		const char *temp;



		if (riscv_of_processor_hartid(node) < 0)

		rc = riscv_of_processor_hartid(node, &hartid);

		if (rc < 0)

			continue;



		if (of_property_read_string(node, "riscv,isa", &isa)) {

arch/riscv/kernel/smpboot.c

+5 −4
Original line number Diff line number Diff line
@@ -72,15 +72,16 @@ void __init smp_prepare_cpus(unsigned int max_cpus) 
void __init setup_smp(void)

{

	struct device_node *dn;

	int hart;

	unsigned long hart;

	bool found_boot_cpu = false;

	int cpuid = 1;

	int rc;



	cpu_set_ops(0);



	for_each_of_cpu_node(dn) {

		hart = riscv_of_processor_hartid(dn);

		if (hart < 0)

		rc = riscv_of_processor_hartid(dn, &hart);

		if (rc < 0)

			continue;



		if (hart == cpuid_to_hartid_map(0)) {
@@ -90,7 +91,7 @@ void __init setup_smp(void) 
			continue;

		}

		if (cpuid >= NR_CPUS) {

			pr_warn("Invalid cpuid [%d] for hartid [%d]\n",

			pr_warn("Invalid cpuid [%d] for hartid [%lu]\n",

				cpuid, hart);

			continue;

		}

drivers/clocksource/timer-riscv.c

+8 −7
Original line number Diff line number Diff line
@@ -101,20 +101,21 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) 


static int __init riscv_timer_init_dt(struct device_node *n)

{

	int cpuid, hartid, error;

	int cpuid, error;

	unsigned long hartid;

	struct device_node *child;

	struct irq_domain *domain;



	hartid = riscv_of_processor_hartid(n);

	if (hartid < 0) {

		pr_warn("Not valid hartid for node [%pOF] error = [%d]\n",

	error = riscv_of_processor_hartid(n, &hartid);

	if (error < 0) {

		pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n",

			n, hartid);

		return hartid;

		return error;

	}



	cpuid = riscv_hartid_to_cpuid(hartid);

	if (cpuid < 0) {

		pr_warn("Invalid cpuid for hartid [%d]\n", hartid);

		pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);

		return cpuid;

	}
@@ -140,7 +141,7 @@ static int __init riscv_timer_init_dt(struct device_node *n) 
		return -ENODEV;

	}



	pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",

	pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n",

	       __func__, cpuid, hartid);

	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);

	if (error) {