Commit ad4c4e41 authored by Lang Cheng's avatar Lang Cheng Committed by Zheng Zengkai
Browse files

RDMA/hns: Prevent le32 from being implicitly converted to u32 

mainline inclusion
from mainline-v5.12-rc1
commit 69455df0
category: bugfix
bugzilla: 174002
CVE:NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=69455df04e12334a51b8e80569cb3dfe4de57373

----------------------------------------------------------------------

Replace BUILD_BUG_ON_ZERO() with BUILD_BUG_ON() to avoid sparse
complaining "restricted __le32 degrades to integer".

Link: https://lore.kernel.org/r/1617354454-47840-10-git-send-email-liweihang@huawei.com


Signed-off-by: default avatarLang Cheng <chenglang@huawei.com>
Signed-off-by: default avatarWeihang Li <liweihang@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Signed-off-by: default avatarwangsirong <wangsirong@huawei.com>
Reviewed-by: default avatarChunZhi Hu <huchunzhi@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 1f46bf20

drivers/infiniband/hw/hns/hns_roce_common.h

+7 −8
Original line number Diff line number Diff line
@@ -48,7 +48,8 @@ 
#define roce_set_field(origin, mask, shift, val)                               \

	do {                                                                   \

		(origin) &= ~cpu_to_le32(mask);                                \

		(origin) |= cpu_to_le32(((u32)(val) << (u32)(shift)) & (mask));     \

		(origin) |=                                                    \

			cpu_to_le32(((u32)(val) << (u32)(shift)) & (mask));    \

	} while (0)



#define roce_set_bit(origin, shift, val)                                       \
@@ -59,9 +60,9 @@ 
#define _hr_reg_enable(ptr, field_type, field_h, field_l)                      \

	({                                                                     \

		const field_type *_ptr = ptr;                                  \

		*((__le32 *)_ptr + (field_h) / 32) |=                          \

			cpu_to_le32(BIT((field_l) % 32)) +                     \

			BUILD_BUG_ON_ZERO((field_h) != (field_l));             \

		*((__le32 *)_ptr + (field_h) / 32) |= cpu_to_le32(             \

			BIT((field_l) % 32) +                                  \

			BUILD_BUG_ON_ZERO((field_h) != (field_l)));            \

	})



#define hr_reg_enable(ptr, field) _hr_reg_enable(ptr, field)
@@ -69,11 +70,9 @@ 
#define _hr_reg_clear(ptr, field_type, field_h, field_l)                       \

	({                                                                     \

		const field_type *_ptr = ptr;                                  \

		BUILD_BUG_ON(((field_h) / 32) != ((field_l) / 32));            \

		*((__le32 *)_ptr + (field_h) / 32) &=                          \

			cpu_to_le32(                                           \

				~GENMASK((field_h) % 32, (field_l) % 32)) +    \

			BUILD_BUG_ON_ZERO(((field_h) / 32) !=                  \

					  ((field_l) / 32));                   \

			~cpu_to_le32(GENMASK((field_h) % 32, (field_l) % 32)); \

	})



#define hr_reg_clear(ptr, field) _hr_reg_clear(ptr, field)