Commit ad482232 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/xehpsdv: Read correct RP_STATE_CAP register 



The RP_STATE_CAP register is no longer part of the MCHBAR on XEHPSDV; this
register is now a per-tile register at GTTMMADDR offset 0x250014.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210805163647.801064-7-matthew.d.roper@intel.com
parent efd330b9

drivers/gpu/drm/i915/gt/intel_rps.c

+3 −1
Original line number Diff line number Diff line
@@ -2141,7 +2141,9 @@ u32 intel_rps_read_state_cap(struct intel_rps *rps) 
	struct drm_i915_private *i915 = rps_to_i915(rps);

	struct intel_uncore *uncore = rps_to_uncore(rps);



	if (IS_GEN9_LP(i915))

	if (IS_XEHPSDV(i915))

		return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP);

	else if (IS_GEN9_LP(i915))

		return intel_uncore_read(uncore, BXT_RP_STATE_CAP);

	else

		return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -4124,6 +4124,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   RPN_CAP_MASK		REG_GENMASK(23, 16)

#define BXT_RP_STATE_CAP        _MMIO(0x138170)

#define GEN9_RP_STATE_LIMITS	_MMIO(0x138148)

#define XEHPSDV_RP_STATE_CAP	_MMIO(0x250014)



/*

 * Logical Context regs