Commit ad45edfb authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Junhao He
Browse files

coresight: etm4x: Do not save/restore Data trace control registers 

mainline inclusion
from mainline-v6.10-rc1
commit 5eb3a0c2c52368cb9902e9a6ea04888e093c487d
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IAKVFA
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=5eb3a0c2c52368cb9902e9a6ea04888e093c487d



--------------------------------

ETM4x doesn't support Data trace on A class CPUs. As such do not access the
Data trace control registers during CPU idle. This could cause problems for
ETE. While at it, remove all references to the Data trace control registers.

Fixes: f188b5e7 ("coresight: etm4x: Save/restore state across CPU low power states")
Reported-by: default avatarYabin Cui <yabinc@google.com>
Reviewed-by: default avatarMike Leach <mike.leach@linaro.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Tested-by: default avatarYabin Cui <yabinc@google.com>
Link: https://lore.kernel.org/r/20240412142702.2882478-3-suzuki.poulose@arm.com


Signed-off-by: default avatarJunhao He <hejunhao3@huawei.com>
parent 33159b9f

drivers/hwtracing/coresight/coresight-etm4x-core.c

+0 −6
Original line number Diff line number Diff line
@@ -1652,9 +1652,6 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) 
	state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);

	if (drvdata->nr_pe_cmp)

		state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);

	state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);

	state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);

	state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);



	for (i = 0; i < drvdata->nrseqstate - 1; i++)

		state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
@@ -1784,9 +1781,6 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) 
	etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);

	if (drvdata->nr_pe_cmp)

		etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);

	etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);

	etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);

	etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);



	for (i = 0; i < drvdata->nrseqstate - 1; i++)

		etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));

drivers/hwtracing/coresight/coresight-etm4x.h

+0 −27
Original line number Diff line number Diff line
@@ -43,9 +43,6 @@ 
#define TRCVIIECTLR			0x084

#define TRCVISSCTLR			0x088

#define TRCVIPCSSCTLR			0x08C

#define TRCVDCTLR			0x0A0

#define TRCVDSACCTLR			0x0A4

#define TRCVDARCCTLR			0x0A8

/* Derived resources registers */

#define TRCSEQEVRn(n)			(0x100 + (n * 4))

#define TRCSEQRSTEVR			0x118
@@ -87,8 +84,6 @@ 
/* Comparator registers */

#define TRCACVRn(n)			(0x400 + (n * 8))

#define TRCACATRn(n)			(0x480 + (n * 8))

#define TRCDVCVRn(n)			(0x500 + (n * 16))

#define TRCDVCMRn(n)			(0x580 + (n * 16))

#define TRCCIDCVRn(n)			(0x600 + (n * 8))

#define TRCVMIDCVRn(n)			(0x640 + (n * 8))

#define TRCCIDCCTLR0			0x680
@@ -169,9 +164,6 @@ 
/* List of registers accessible via System instructions */

#define ETM4x_ONLY_SYSREG_LIST(op, val)		\

	CASE_##op((val), TRCPROCSELR)		\

	CASE_##op((val), TRCVDCTLR)		\

	CASE_##op((val), TRCVDSACCTLR)		\

	CASE_##op((val), TRCVDARCCTLR)		\

	CASE_##op((val), TRCOSLAR)



#define ETM_COMMON_SYSREG_LIST(op, val)		\
@@ -319,22 +311,6 @@ 
	CASE_##op((val), TRCACATRn(13))		\

	CASE_##op((val), TRCACATRn(14))		\

	CASE_##op((val), TRCACATRn(15))		\

	CASE_##op((val), TRCDVCVRn(0))		\

	CASE_##op((val), TRCDVCVRn(1))		\

	CASE_##op((val), TRCDVCVRn(2))		\

	CASE_##op((val), TRCDVCVRn(3))		\

	CASE_##op((val), TRCDVCVRn(4))		\

	CASE_##op((val), TRCDVCVRn(5))		\

	CASE_##op((val), TRCDVCVRn(6))		\

	CASE_##op((val), TRCDVCVRn(7))		\

	CASE_##op((val), TRCDVCMRn(0))		\

	CASE_##op((val), TRCDVCMRn(1))		\

	CASE_##op((val), TRCDVCMRn(2))		\

	CASE_##op((val), TRCDVCMRn(3))		\

	CASE_##op((val), TRCDVCMRn(4))		\

	CASE_##op((val), TRCDVCMRn(5))		\

	CASE_##op((val), TRCDVCMRn(6))		\

	CASE_##op((val), TRCDVCMRn(7))		\

	CASE_##op((val), TRCCIDCVRn(0))		\

	CASE_##op((val), TRCCIDCVRn(1))		\

	CASE_##op((val), TRCCIDCVRn(2))		\
@@ -807,9 +783,6 @@ struct etmv4_save_state { 
	u32	trcviiectlr;

	u32	trcvissctlr;

	u32	trcvipcssctlr;

	u32	trcvdctlr;

	u32	trcvdsacctlr;

	u32	trcvdarcctlr;



	u32	trcseqevr[ETM_MAX_SEQ_STATES];

	u32	trcseqrstevr;