Commit ad42d5fc authored by Kim Phillips's avatar Kim Phillips Committed by Herbert Xu
Browse files

crypto: talitos - prepare driver for channel remap support 



Add a reg member to the channel struct and use it to
access channels.

Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 5b859b6e

drivers/crypto/talitos.c

+22 −15
Original line number Diff line number Diff line
@@ -99,6 +99,8 @@ struct talitos_request { 


/* per-channel fifo management */

struct talitos_channel {

	void __iomem *reg;



	/* request fifo */

	struct talitos_request *fifo;
@@ -197,9 +199,9 @@ static int reset_channel(struct device *dev, int ch) 
	struct talitos_private *priv = dev_get_drvdata(dev);

	unsigned int timeout = TALITOS_TIMEOUT;



	setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);

	setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);



	while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)

	while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)

	       && --timeout)

		cpu_relax();
@@ -209,12 +211,12 @@ static int reset_channel(struct device *dev, int ch) 
	}



	/* set 36-bit addressing, done writeback enable and done IRQ enable */

	setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_EAE |

	setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |

		  TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);



	/* and ICCR writeback, if available */

	if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)

		setbits32(priv->reg + TALITOS_CCCR_LO(ch),

		setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,

		          TALITOS_CCCR_LO_IWSE);



	return 0;
@@ -328,8 +330,9 @@ static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc, 


	/* GO! */

	wmb();

	out_be32(priv->reg + TALITOS_FF(ch), upper_32_bits(request->dma_desc));

	out_be32(priv->reg + TALITOS_FF_LO(ch),

	out_be32(priv->chan[ch].reg + TALITOS_FF,

		 upper_32_bits(request->dma_desc));

	out_be32(priv->chan[ch].reg + TALITOS_FF_LO,

		 lower_32_bits(request->dma_desc));



	spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
@@ -423,7 +426,7 @@ static u32 current_desc_hdr(struct device *dev, int ch) 
	int tail = priv->chan[ch].tail;

	dma_addr_t cur_desc;



	cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));

	cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);



	while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {

		tail = (tail + 1) & (priv->fifo_len - 1);
@@ -445,7 +448,7 @@ static void report_eu_error(struct device *dev, int ch, u32 desc_hdr) 
	int i;



	if (!desc_hdr)

		desc_hdr = in_be32(priv->reg + TALITOS_DESCBUF(ch));

		desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);



	switch (desc_hdr & DESC_HDR_SEL0_MASK) {

	case DESC_HDR_SEL0_AFEU:
@@ -507,8 +510,8 @@ static void report_eu_error(struct device *dev, int ch, u32 desc_hdr) 


	for (i = 0; i < 8; i++)

		dev_err(dev, "DESCBUF 0x%08x_%08x\n",

			in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),

			in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));

			in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),

			in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));

}



/*
@@ -529,8 +532,8 @@ static void talitos_error(unsigned long data, u32 isr, u32 isr_lo) 


		error = -EINVAL;



		v = in_be32(priv->reg + TALITOS_CCPSR(ch));

		v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));

		v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);

		v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);



		if (v_lo & TALITOS_CCPSR_LO_DOF) {

			dev_err(dev, "double fetch fifo overflow error\n");
@@ -568,10 +571,10 @@ static void talitos_error(unsigned long data, u32 isr, u32 isr_lo) 
		if (reset_ch) {

			reset_channel(dev, ch);

		} else {

			setbits32(priv->reg + TALITOS_CCCR(ch),

			setbits32(priv->chan[ch].reg + TALITOS_CCCR,

				  TALITOS_CCCR_CONT);

			setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);

			while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &

			setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);

			while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &

			       TALITOS_CCCR_CONT) && --timeout)

				cpu_relax();

			if (timeout == 0) {
@@ -2710,6 +2713,10 @@ static int talitos_probe(struct platform_device *ofdev) 
		goto err_out;

	}



	for (i = 0; i < priv->num_channels; i++)

		priv->chan[i].reg = priv->reg + TALITOS_CH_BASE_OFFSET +

				    TALITOS_CH_STRIDE * (i + 1);



	for (i = 0; i < priv->num_channels; i++) {

		spin_lock_init(&priv->chan[i].head_lock);

		spin_lock_init(&priv->chan[i].tail_lock);

drivers/crypto/talitos.h

+16 −15
Original line number Diff line number Diff line 
/*

 * Freescale SEC (talitos) device register and descriptor header defines

 *

 * Copyright (c) 2006-2010 Freescale Semiconductor, Inc.

 * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions
@@ -49,13 +49,14 @@ 
#define TALITOS_ICR_LO			0x101C



/* channel register address stride */

#define TALITOS_CH_BASE_OFFSET		0x1000	/* default channel map base */

#define TALITOS_CH_STRIDE		0x100



/* channel configuration register  */

#define TALITOS_CCCR(ch)		(ch * TALITOS_CH_STRIDE + 0x1108)

#define TALITOS_CCCR			0x8

#define   TALITOS_CCCR_CONT		0x2    /* channel continue */

#define   TALITOS_CCCR_RESET		0x1    /* channel reset */

#define TALITOS_CCCR_LO(ch)		(ch * TALITOS_CH_STRIDE + 0x110c)

#define TALITOS_CCCR_LO			0xc

#define   TALITOS_CCCR_LO_IWSE		0x80   /* chan. ICCR writeback enab. */

#define   TALITOS_CCCR_LO_EAE		0x20   /* extended address enable */

#define   TALITOS_CCCR_LO_CDWE		0x10   /* chan. done writeback enab. */
@@ -63,8 +64,8 @@ 
#define   TALITOS_CCCR_LO_CDIE		0x2    /* channel done IRQ enable */



/* CCPSR: channel pointer status register */

#define TALITOS_CCPSR(ch)		(ch * TALITOS_CH_STRIDE + 0x1110)

#define TALITOS_CCPSR_LO(ch)		(ch * TALITOS_CH_STRIDE + 0x1114)

#define TALITOS_CCPSR			0x10

#define TALITOS_CCPSR_LO		0x14

#define   TALITOS_CCPSR_LO_DOF		0x8000 /* double FF write oflow error */

#define   TALITOS_CCPSR_LO_SOF		0x4000 /* single FF write oflow error */

#define   TALITOS_CCPSR_LO_MDTE		0x2000 /* master data transfer error */
@@ -79,24 +80,24 @@ 
#define   TALITOS_CCPSR_LO_SRL		0x0010 /* scatter return/length error */



/* channel fetch fifo register */

#define TALITOS_FF(ch)			(ch * TALITOS_CH_STRIDE + 0x1148)

#define TALITOS_FF_LO(ch)		(ch * TALITOS_CH_STRIDE + 0x114c)

#define TALITOS_FF			0x48

#define TALITOS_FF_LO			0x4c



/* current descriptor pointer register */

#define TALITOS_CDPR(ch)		(ch * TALITOS_CH_STRIDE + 0x1140)

#define TALITOS_CDPR_LO(ch)		(ch * TALITOS_CH_STRIDE + 0x1144)

#define TALITOS_CDPR			0x40

#define TALITOS_CDPR_LO			0x44



/* descriptor buffer register */

#define TALITOS_DESCBUF(ch)		(ch * TALITOS_CH_STRIDE + 0x1180)

#define TALITOS_DESCBUF_LO(ch)		(ch * TALITOS_CH_STRIDE + 0x1184)

#define TALITOS_DESCBUF			0x80

#define TALITOS_DESCBUF_LO		0x84



/* gather link table */

#define TALITOS_GATHER(ch)		(ch * TALITOS_CH_STRIDE + 0x11c0)

#define TALITOS_GATHER_LO(ch)		(ch * TALITOS_CH_STRIDE + 0x11c4)

#define TALITOS_GATHER			0xc0

#define TALITOS_GATHER_LO		0xc4



/* scatter link table */

#define TALITOS_SCATTER(ch)		(ch * TALITOS_CH_STRIDE + 0x11e0)

#define TALITOS_SCATTER_LO(ch)		(ch * TALITOS_CH_STRIDE + 0x11e4)

#define TALITOS_SCATTER			0xe0

#define TALITOS_SCATTER_LO		0xe4



/* execution unit interrupt status registers */

#define TALITOS_DEUISR			0x2030 /* DES unit */