Commit ad3b0d33 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/fifo: turn chan subdev mask into engine mask 



This data is used to know which engines/classes are reachable on a given
channel's runlist, and needs to be replaced with something that doesn't
rely on subdev index.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent 49616203

drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h

+1 −1
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ struct nvkm_fifo_engn { 
struct nvkm_fifo_chan {

	const struct nvkm_fifo_chan_func *func;

	struct nvkm_fifo *fifo;

	u64 engines;

	u32 engm;

	struct nvkm_object object;



	struct list_head head;

drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h

+0 −1
Original line number Diff line number Diff line
@@ -27,7 +27,6 @@ u32 nvkm_top_reset(struct nvkm_device *, enum nvkm_subdev_type, int); 
u32 nvkm_top_intr_mask(struct nvkm_device *, enum nvkm_subdev_type, int);

int nvkm_top_fault_id(struct nvkm_device *, enum nvkm_devidx);

enum nvkm_devidx nvkm_top_fault(struct nvkm_device *, int fault);

enum nvkm_devidx nvkm_top_engine(struct nvkm_device *, int, int *runl, int *engn);



int gk104_top_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_top **);

#endif

drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c

+6 −7
Original line number Diff line number Diff line
@@ -212,13 +212,12 @@ nvkm_fifo_chan_child_get(struct nvkm_object *object, int index, 
{

	struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object);

	struct nvkm_fifo *fifo = chan->fifo;

	struct nvkm_device *device = fifo->engine.subdev.device;

	struct nvkm_engine *engine;

	u64 mask = chan->engines;

	int ret, i, c;

	u32 engm = chan->engm;

	int engi, ret, c;



	for (; c = 0, i = __ffs64(mask), mask; mask &= ~(1ULL << i)) {

		if (!(engine = nvkm_device_engine(device, i, 0)))

	for (; c = 0, engi = __ffs(engm), engm; engm &= ~(1ULL << engi)) {

		if (!(engine = fifo->func->id_engine(fifo, engi)))

			continue;

		oclass->engine = engine;

		oclass->base.oclass = 0;
@@ -361,7 +360,7 @@ nvkm_fifo_chan_func = { 
int

nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func,

		    struct nvkm_fifo *fifo, u32 size, u32 align, bool zero,

		    u64 hvmm, u64 push, u64 engines, int bar, u32 base,

		    u64 hvmm, u64 push, u32 engm, int bar, u32 base,

		    u32 user, const struct nvkm_oclass *oclass,

		    struct nvkm_fifo_chan *chan)

{
@@ -374,7 +373,7 @@ nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, 
	nvkm_object_ctor(&nvkm_fifo_chan_func, oclass, &chan->object);

	chan->func = func;

	chan->fifo = fifo;

	chan->engines = engines;

	chan->engm = engm;

	INIT_LIST_HEAD(&chan->head);



	/* instance memory */

drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ struct nvkm_fifo_chan_func { 


int nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *, struct nvkm_fifo *,

			u32 size, u32 align, bool zero, u64 vm, u64 push,

			u64 engines, int bar, u32 base, u32 user,

			u32 engm, int bar, u32 base, u32 user,

			const struct nvkm_oclass *, struct nvkm_fifo_chan *);



struct nvkm_fifo_chan_oclass {

drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c

+14 −14
Original line number Diff line number Diff line
@@ -220,20 +220,20 @@ g84_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vmm, u64 push, 


	ret = nvkm_fifo_chan_ctor(&g84_fifo_chan_func, &fifo->base,

				  0x10000, 0x1000, false, vmm, push,

				  (1ULL << NVKM_ENGINE_BSP) |

				  (1ULL << NVKM_ENGINE_CE0) |

				  (1ULL << NVKM_ENGINE_CIPHER) |

				  (1ULL << NVKM_ENGINE_DMAOBJ) |

				  (1ULL << NVKM_ENGINE_GR) |

				  (1ULL << NVKM_ENGINE_ME) |

				  (1ULL << NVKM_ENGINE_MPEG) |

				  (1ULL << NVKM_ENGINE_MSPDEC) |

				  (1ULL << NVKM_ENGINE_MSPPP) |

				  (1ULL << NVKM_ENGINE_MSVLD) |

				  (1ULL << NVKM_ENGINE_SEC) |

				  (1ULL << NVKM_ENGINE_SW) |

				  (1ULL << NVKM_ENGINE_VIC) |

				  (1ULL << NVKM_ENGINE_VP),

				  BIT(G84_FIFO_ENGN_SW) |

				  BIT(G84_FIFO_ENGN_GR) |

				  BIT(G84_FIFO_ENGN_MPEG) |

				  BIT(G84_FIFO_ENGN_MSPPP) |

				  BIT(G84_FIFO_ENGN_ME) |

				  BIT(G84_FIFO_ENGN_CE0) |

				  BIT(G84_FIFO_ENGN_VP) |

				  BIT(G84_FIFO_ENGN_MSPDEC) |

				  BIT(G84_FIFO_ENGN_CIPHER) |

				  BIT(G84_FIFO_ENGN_SEC) |

				  BIT(G84_FIFO_ENGN_VIC) |

				  BIT(G84_FIFO_ENGN_BSP) |

				  BIT(G84_FIFO_ENGN_MSVLD) |

				  BIT(G84_FIFO_ENGN_DMA),

				  0, 0xc00000, 0x2000, oclass, &chan->base);

	chan->fifo = fifo;

	if (ret)