Unverified Commit ad0e1bdf authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!6868 irqchip/loongson-pch-pic: Update interrupt registration policy 

Merge Pull Request from: @ci-robot 
 
PR sync from: Hongchen Zhang <zhanghongchen@loongson.cn>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/FGOOQZTYNMP3QEEEMHJVDI4RCJW77HO4/ 
 
https://gitee.com/openeuler/kernel/issues/I9N1XJ 
 
Link:https://gitee.com/openeuler/kernel/pulls/6868

 

Reviewed-by: default avatarJuxin Gao <gaojuxin@loongson.cn>
Signed-off-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
parents d7264a59 a0636064

drivers/irqchip/irq-loongson-pch-pic.c

+56 −14
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
#define PIC_COUNT		(PIC_COUNT_PER_REG * PIC_REG_COUNT)

#define PIC_REG_IDX(irq_id)	((irq_id) / PIC_COUNT_PER_REG)

#define PIC_REG_BIT(irq_id)	((irq_id) % PIC_COUNT_PER_REG)

#define PIC_UNDEF_VECTOR	255

#define PIC_COUNT_PER_REG64	64

#define PIC_REG64_COUNT		1

#define PIC_REG64_IDX(irq_id)	((irq_id) / PIC_COUNT_PER_REG64)
@@ -50,6 +51,8 @@ struct pch_pic { 
	u32			saved_vec_en[PIC_REG_COUNT];

	u32			saved_vec_pol[PIC_REG_COUNT];

	u32			saved_vec_edge[PIC_REG_COUNT];

	u8			table[PIC_COUNT];

	int			inuse;

};



static struct pch_pic *pch_pic_priv[MAX_IO_PICS];
@@ -61,6 +64,11 @@ struct irq_domain *get_pchpic_irq_domain(void) 
	return pch_pic_priv[0]->pic_domain;

}



static inline u8 hwirq_to_bit(struct pch_pic *priv, int hirq)

{

	return priv->table[hirq];

}



static void pch_pic_bitset(struct pch_pic *priv, int offset, int bit)

{

	u32 reg;
@@ -89,45 +97,47 @@ static void pch_pic_mask_irq(struct irq_data *d) 
{

	struct pch_pic *priv = irq_data_get_irq_chip_data(d);



	pch_pic_bitset(priv, PCH_PIC_MASK, d->hwirq);

	pch_pic_bitset(priv, PCH_PIC_MASK, hwirq_to_bit(priv, d->hwirq));

	irq_chip_mask_parent(d);

}



static void pch_pic_unmask_irq(struct irq_data *d)

{

	struct pch_pic *priv = irq_data_get_irq_chip_data(d);

	int bit = hwirq_to_bit(priv, d->hwirq);



	writeq(BIT(PIC_REG64_BIT(d->hwirq)),

			priv->base + PCH_PIC_CLR + PIC_REG64_IDX(d->hwirq) * 8);

			priv->base + PCH_PIC_CLR + PIC_REG64_IDX(bit) * 8);



	irq_chip_unmask_parent(d);

	pch_pic_bitclr(priv, PCH_PIC_MASK, d->hwirq);

	pch_pic_bitclr(priv, PCH_PIC_MASK, bit);

}



static int pch_pic_set_type(struct irq_data *d, unsigned int type)

{

	struct pch_pic *priv = irq_data_get_irq_chip_data(d);

	int bit = hwirq_to_bit(priv, d->hwirq);

	int ret = 0;



	switch (type) {

	case IRQ_TYPE_EDGE_RISING:

		pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq);

		pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq);

		pch_pic_bitset(priv, PCH_PIC_EDGE, bit);

		pch_pic_bitclr(priv, PCH_PIC_POL, bit);

		irq_set_handler_locked(d, handle_edge_irq);

		break;

	case IRQ_TYPE_EDGE_FALLING:

		pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq);

		pch_pic_bitset(priv, PCH_PIC_POL, d->hwirq);

		pch_pic_bitset(priv, PCH_PIC_EDGE, bit);

		pch_pic_bitset(priv, PCH_PIC_POL, bit);

		irq_set_handler_locked(d, handle_edge_irq);

		break;

	case IRQ_TYPE_LEVEL_HIGH:

		pch_pic_bitclr(priv, PCH_PIC_EDGE, d->hwirq);

		pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq);

		pch_pic_bitclr(priv, PCH_PIC_EDGE, bit);

		pch_pic_bitclr(priv, PCH_PIC_POL, bit);

		irq_set_handler_locked(d, handle_level_irq);

		break;

	case IRQ_TYPE_LEVEL_LOW:

		pch_pic_bitclr(priv, PCH_PIC_EDGE, d->hwirq);

		pch_pic_bitset(priv, PCH_PIC_POL, d->hwirq);

		pch_pic_bitclr(priv, PCH_PIC_EDGE, bit);

		pch_pic_bitset(priv, PCH_PIC_POL, bit);

		irq_set_handler_locked(d, handle_level_irq);

		break;

	default:
@@ -142,11 +152,12 @@ static void pch_pic_ack_irq(struct irq_data *d) 
{

	unsigned int reg;

	struct pch_pic *priv = irq_data_get_irq_chip_data(d);

	int bit = hwirq_to_bit(priv, d->hwirq);



	reg = readl(priv->base + PCH_PIC_EDGE + PIC_REG_IDX(d->hwirq) * 4);

	reg = readl(priv->base + PCH_PIC_EDGE + PIC_REG_IDX(bit) * 4);

	if (reg & BIT(PIC_REG_BIT(d->hwirq))) {

		writeq(BIT(PIC_REG64_BIT(d->hwirq)),

			priv->base + PCH_PIC_CLR + PIC_REG64_IDX(d->hwirq) * 8);

			priv->base + PCH_PIC_CLR + PIC_REG64_IDX(bit) * 8);

	}

	irq_chip_ack_parent(d);

}
@@ -168,6 +179,8 @@ static int pch_pic_domain_translate(struct irq_domain *d, 
{

	struct pch_pic *priv = d->host_data;

	struct device_node *of_node = to_of_node(fwspec->fwnode);

	unsigned long flags;

	int i;



	if (of_node) {

		if (fwspec->param_count < 2)
@@ -180,12 +193,33 @@ static int pch_pic_domain_translate(struct irq_domain *d, 
			return -EINVAL;



		*hwirq = fwspec->param[0] - priv->gsi_base;



		if (fwspec->param_count > 1)

			*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;

		else

			*type = IRQ_TYPE_NONE;

	}



	raw_spin_lock_irqsave(&priv->pic_lock, flags);

	/* Check pic-table to confirm if the hwirq has been assigned */

	for (i = 0; i < priv->inuse; i++) {

		if (priv->table[i] == *hwirq) {

			*hwirq = i;

			break;

		}

	}

	if (i == priv->inuse) {

		/* Assign a new hwirq in pic-table */

		if (priv->inuse >= PIC_COUNT) {

			pr_err("pch-pic domain has no free vectors\n");

			raw_spin_unlock_irqrestore(&priv->pic_lock, flags);

			return -EINVAL;

		}

		priv->table[priv->inuse] = *hwirq;

		*hwirq = priv->inuse++;

	}

	raw_spin_unlock_irqrestore(&priv->pic_lock, flags);



	return 0;

}
@@ -203,6 +237,9 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq, 
	if (err)

		return err;



	/* Write vector ID */

	writeb(priv->ht_vec_base + hwirq, priv->base + PCH_INT_HTVEC(hwirq_to_bit(priv, hwirq)));



	parent_fwspec.fwnode = domain->parent->fwnode;

	parent_fwspec.param_count = 1;

	parent_fwspec.param[0] = hwirq + priv->ht_vec_base;
@@ -231,7 +268,7 @@ static void pch_pic_reset(struct pch_pic *priv) 


	for (i = 0; i < PIC_COUNT; i++) {

		/* Write vector ID */

		writeb(priv->ht_vec_base + i, priv->base + PCH_INT_HTVEC(i));

		writeb(priv->ht_vec_base + i, priv->base + PCH_INT_HTVEC(hwirq_to_bit(priv, i)));

		/* Hardcode route to HT0 Lo */

		writeb(1, priv->base + PCH_INT_ROUTE(i));

	}
@@ -295,6 +332,7 @@ static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base, 
			u32 gsi_base)

{

	struct pch_pic *priv;

	int i;



	priv = kzalloc(sizeof(*priv), GFP_KERNEL);

	if (!priv)
@@ -305,6 +343,10 @@ static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base, 
	if (!priv->base)

		goto free_priv;



	priv->inuse = 0;

	for (i = 0; i < PIC_COUNT; i++)

		priv->table[i] = PIC_UNDEF_VECTOR;



	priv->ht_vec_base = vec_base;

	priv->vec_count = ((readq(priv->base) >> 48) & 0xff) + 1;

	priv->gsi_base = gsi_base;