Commit ad04cc05 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
Browse files

bnxt_en: Update firmware interface to 1.10.2.95 



The main changes are timestamp support for all RX packets and new PCIe
statistics.

Signed-off-by: default avatarMichael Chan <michael.chan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 9e2bc267

drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h

+280 −135
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
 *

 * Copyright (c) 2014-2016 Broadcom Corporation

 * Copyright (c) 2014-2018 Broadcom Limited

 * Copyright (c) 2018-2021 Broadcom Inc.

 * Copyright (c) 2018-2022 Broadcom Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by
@@ -311,6 +311,8 @@ struct cmd_nums { 
	#define HWRM_CFA_TFLIB                            0x125UL

	#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR            0x126UL

	#define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR          0x127UL

	#define HWRM_CFA_TLS_FILTER_ALLOC                 0x128UL

	#define HWRM_CFA_TLS_FILTER_FREE                  0x129UL

	#define HWRM_ENGINE_CKV_STATUS                    0x12eUL

	#define HWRM_ENGINE_CKV_CKEK_ADD                  0x12fUL

	#define HWRM_ENGINE_CKV_CKEK_DELETE               0x130UL
@@ -375,6 +377,8 @@ struct cmd_nums { 
	#define HWRM_FUNC_DBR_PACING_QCFG                 0x1a6UL

	#define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT      0x1a7UL

	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2          0x1a8UL

	#define HWRM_FUNC_DBR_PACING_NQLIST_QUERY         0x1a9UL

	#define HWRM_FUNC_DBR_RECOVERY_COMPLETED          0x1aaUL

	#define HWRM_SELFTEST_QLIST                       0x200UL

	#define HWRM_SELFTEST_EXEC                        0x201UL

	#define HWRM_SELFTEST_IRQ                         0x202UL
@@ -399,6 +403,7 @@ struct cmd_nums { 
	#define HWRM_MFG_PSOC_QSTATUS                     0x215UL

	#define HWRM_MFG_SELFTEST_QLIST                   0x216UL

	#define HWRM_MFG_SELFTEST_EXEC                    0x217UL

	#define HWRM_STAT_GENERIC_QSTATS                  0x218UL

	#define HWRM_TF                                   0x2bcUL

	#define HWRM_TF_VERSION_GET                       0x2bdUL

	#define HWRM_TF_SESSION_OPEN                      0x2c6UL
@@ -541,8 +546,8 @@ struct hwrm_err_output { 
#define HWRM_VERSION_MAJOR 1

#define HWRM_VERSION_MINOR 10

#define HWRM_VERSION_UPDATE 2

#define HWRM_VERSION_RSVD 73

#define HWRM_VERSION_STR "1.10.2.73"

#define HWRM_VERSION_RSVD 95

#define HWRM_VERSION_STR "1.10.2.95"



/* hwrm_ver_get_input (size:192b/24B) */

struct hwrm_ver_get_input {
@@ -770,7 +775,9 @@ struct hwrm_async_event_cmpl { 
	#define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP              0x44UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT               0x45UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD  0x46UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID          0x47UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE                 0x47UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE  0x48UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID          0x49UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG               0xfeUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR                 0xffUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_LAST                      ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
@@ -1259,7 +1266,8 @@ struct hwrm_async_event_cmpl_error_report_base { 
	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL           0x2UL

	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM                      0x3UL

	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD  0x4UL

	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST                    ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD

	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD        0x5UL

	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST                    ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD

};



/* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */
@@ -1365,6 +1373,8 @@ struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { 
	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT                    0

	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD  0x4UL

	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST                    ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD

	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK                        0xffffff00UL

	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT                         8

};



/* hwrm_func_reset_input (size:192b/24B) */
@@ -1630,6 +1640,8 @@ struct hwrm_func_qcaps_output { 
	#define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED                              0x8000000UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED                     0x10000000UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED                        0x20000000UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED                 0x40000000UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED     0x80000000UL

	u8	max_schqs;

	u8	mpc_chnls_cap;

	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE         0x1UL
@@ -1638,7 +1650,23 @@ struct hwrm_func_qcaps_output { 
	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA      0x8UL

	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE     0x10UL

	__le16	max_key_ctxs_alloc;

	u8	unused_1[7];

	__le32	flags_ext2;

	#define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED     0x1UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED                       0x2UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED                      0x4UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED             0x8UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED       0x10UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED              0x20UL

	__le16	tunnel_disable_flag;

	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN      0x1UL

	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE        0x2UL

	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE      0x4UL

	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE      0x8UL

	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE        0x10UL

	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP     0x20UL

	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS       0x40UL

	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE      0x80UL

	u8	unused_1;

	u8	valid;

};
@@ -1802,11 +1830,17 @@ struct hwrm_func_qcfg_output { 
	__le16	host_mtu;

	__le16	alloc_tx_key_ctxs;

	__le16	alloc_rx_key_ctxs;

	u8	unused_3[5];

	u8	port_kdnet_mode;

	#define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL

	#define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED  0x1UL

	#define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST    FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED

	u8	kdnet_pcie_function;

	__le16	port_kdnet_fid;

	u8	unused_3;

	u8	valid;

};



/* hwrm_func_cfg_input (size:896b/112B) */

/* hwrm_func_cfg_input (size:960b/120B) */

struct hwrm_func_cfg_input {

	__le16	req_type;

	__le16	cmpl_ring;
@@ -1986,7 +2020,13 @@ struct hwrm_func_cfg_input { 
	__le16	host_mtu;

	__le16	num_tx_key_ctxs;

	__le16	num_rx_key_ctxs;

	u8	unused_0[4];

	__le32	enables2;

	#define FUNC_CFG_REQ_ENABLES2_KDNET     0x1UL

	u8	port_kdnet_mode;

	#define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL

	#define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED  0x1UL

	#define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST    FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED

	u8	unused_0[7];

};



/* hwrm_func_cfg_output (size:128b/16B) */
@@ -3367,6 +3407,12 @@ struct hwrm_func_backing_store_cfg_v2_input { 
	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TKC           0x13UL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RKC           0x14UL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING   0x15UL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW  0x16UL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW  0x17UL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW  0x19UL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_TKC      0x1aUL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_RKC      0x1bUL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID       0xffffUL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST         FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID

	__le16	instance;
@@ -3428,6 +3474,12 @@ struct hwrm_func_backing_store_qcfg_v2_input { 
	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TKC           0x13UL

	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RKC           0x14UL

	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING   0x15UL

	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW  0x16UL

	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW  0x17UL

	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL

	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW  0x19UL

	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_TKC      0x1aUL

	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_RKC      0x1bUL

	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID       0xffffUL

	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST         FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID

	__le16	instance;
@@ -3453,6 +3505,8 @@ struct hwrm_func_backing_store_qcfg_v2_output { 
	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TKC         0x13UL

	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RKC         0x14UL

	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL

	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_TKC    0x1aUL

	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_RKC    0x1bUL

	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID     0xffffUL

	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST       FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID

	__le16	instance;
@@ -3540,6 +3594,12 @@ struct hwrm_func_backing_store_qcaps_v2_input { 
	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC           0x13UL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC           0x14UL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING   0x15UL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW  0x16UL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW  0x17UL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW  0x19UL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC      0x1aUL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC      0x1bUL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID       0xffffUL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST         FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID

	u8	rsvd[6];
@@ -3564,12 +3624,19 @@ struct hwrm_func_backing_store_qcaps_v2_output { 
	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TKC           0x13UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RKC           0x14UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING   0x15UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW  0x16UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW  0x17UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW  0x19UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_TKC      0x1aUL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_RKC      0x1bUL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID       0xffffUL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST         FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID

	__le16	entry_size;

	__le32	flags;

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT      0x1UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID                0x2UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY     0x4UL

	__le32	instance_bit_map;

	u8	ctx_init_value;

	u8	ctx_init_offset;
@@ -4108,6 +4175,8 @@ struct hwrm_port_mac_cfg_input { 
	#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE        0x800UL

	#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE           0x1000UL

	#define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS            0x2000UL

	#define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE      0x4000UL

	#define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE     0x8000UL

	__le32	enables;

	#define PORT_MAC_CFG_REQ_ENABLES_IPG                            0x1UL

	#define PORT_MAC_CFG_REQ_ENABLES_LPBK                           0x2UL
@@ -6390,6 +6459,7 @@ struct hwrm_vnic_cfg_input { 
	#define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID     0x40UL

	#define VNIC_CFG_REQ_ENABLES_QUEUE_ID                 0x80UL

	#define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE          0x100UL

	#define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE              0x200UL

	__le16	vnic_id;

	__le16	dflt_ring_grp;

	__le16	rss_rule;
@@ -6404,7 +6474,12 @@ struct hwrm_vnic_cfg_input { 
	#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK  0x1UL

	#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX     0x2UL

	#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST   VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX

	u8	unused0[5];

	u8	l2_cqe_mode;

	#define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT    0x0UL

	#define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL

	#define VNIC_CFG_REQ_L2_CQE_MODE_MIXED      0x2UL

	#define VNIC_CFG_REQ_L2_CQE_MODE_LAST      VNIC_CFG_REQ_L2_CQE_MODE_MIXED

	u8	unused0[4];

};



/* hwrm_vnic_cfg_output (size:128b/16B) */
@@ -6452,10 +6527,16 @@ struct hwrm_vnic_qcaps_output { 
	#define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP                     0x1000UL

	#define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP                0x2000UL

	#define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP                 0x4000UL

	#define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_FUNCTION_TOEPLITZ_CAP      0x8000UL

	#define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_FUNCTION_XOR_CAP           0x10000UL

	#define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_FUNCTION_CHKSM_CAP         0x20000UL

	#define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP           0x8000UL

	#define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP                0x10000UL

	#define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP     0x20000UL

	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP                 0x40000UL

	#define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP                          0x80000UL

	#define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP                         0x100000UL

	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP               0x200000UL

	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP              0x400000UL

	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP               0x800000UL

	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP              0x1000000UL

	__le16	max_aggs_supported;

	u8	unused_1[5];

	u8	valid;
@@ -6576,6 +6657,10 @@ struct hwrm_vnic_rss_cfg_input { 
	#define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6            0x10UL

	#define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6            0x20UL

	#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL     0x40UL

	#define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4         0x80UL

	#define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4        0x100UL

	#define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6         0x200UL

	#define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6        0x400UL

	__le16	vnic_id;

	u8	ring_table_pair_index;

	u8	hash_mode_flags;
@@ -6590,11 +6675,11 @@ struct hwrm_vnic_rss_cfg_input { 
	u8	flags;

	#define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE     0x1UL

	#define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE     0x2UL

	u8	rss_hash_function;

	#define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_TOEPLITZ 0x0UL

	#define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_XOR      0x1UL

	#define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_CHECKSUM 0x2UL

	#define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_LAST    VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_CHECKSUM

	u8	ring_select_mode;

	#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ          0x0UL

	#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR               0x1UL

	#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL

	#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST             VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM

	u8	unused_1[4];

};
@@ -6740,6 +6825,8 @@ struct hwrm_ring_alloc_input { 
	#define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST    RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX

	__le16	flags;

	#define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD                        0x1UL

	#define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION     0x2UL

	#define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING                     0x4UL

	__le64	page_tbl_addr;

	__le32	fbo;

	u8	page_size;
@@ -7924,11 +8011,16 @@ struct hwrm_cfa_flow_info_input { 
	__le64	resp_addr;

	__le16	flow_handle;

	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK      0xfffUL

	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT        0

	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT       0x1000UL

	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT    0x2000UL

	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_TX        0x3000UL

	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT    0x4000UL

	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX        0x8000UL

	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT_RX    0x9000UL

	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT_RX 0xa000UL

	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_RX        0xb000UL

	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 0xc000UL

	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_LAST         CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX

	u8	unused_0[6];

	__le64	ext_flow_handle;

};
@@ -8017,7 +8109,8 @@ struct hwrm_cfa_flow_stats_output { 
	__le64	byte_7;

	__le64	byte_8;

	__le64	byte_9;

	u8	unused_0[7];

	__le16	flow_hits;

	u8	unused_0[5];

	u8	valid;

};
@@ -8243,6 +8336,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 
	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED     0x10000UL

	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED                                0x20000UL

	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED               0x40000UL

	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED                     0x80000UL

	u8	unused_0[3];

	u8	valid;

};
@@ -8583,6 +8677,56 @@ struct pcie_ctx_hw_stats { 
	__le64	pcie_recovery_histogram;

};



/* hwrm_stat_generic_qstats_input (size:256b/32B) */

struct hwrm_stat_generic_qstats_input {

	__le16	req_type;

	__le16	cmpl_ring;

	__le16	seq_id;

	__le16	target_id;

	__le64	resp_addr;

	__le16	generic_stat_size;

	u8	flags;

	#define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER      0x0UL

	#define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL

	#define STAT_GENERIC_QSTATS_REQ_FLAGS_LAST        STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK

	u8	unused_0[5];

	__le64	generic_stat_host_addr;

};



/* hwrm_stat_generic_qstats_output (size:128b/16B) */

struct hwrm_stat_generic_qstats_output {

	__le16	error_code;

	__le16	req_type;

	__le16	seq_id;

	__le16	resp_len;

	__le16	generic_stat_size;

	u8	unused_0[5];

	u8	valid;

};



/* generic_sw_hw_stats (size:1216b/152B) */

struct generic_sw_hw_stats {

	__le64	pcie_statistics_tx_tlp;

	__le64	pcie_statistics_rx_tlp;

	__le64	pcie_credit_fc_hdr_posted;

	__le64	pcie_credit_fc_hdr_nonposted;

	__le64	pcie_credit_fc_hdr_cmpl;

	__le64	pcie_credit_fc_data_posted;

	__le64	pcie_credit_fc_data_nonposted;

	__le64	pcie_credit_fc_data_cmpl;

	__le64	pcie_credit_fc_tgt_nonposted;

	__le64	pcie_credit_fc_tgt_data_posted;

	__le64	pcie_credit_fc_tgt_hdr_posted;

	__le64	pcie_credit_fc_cmpl_hdr_posted;

	__le64	pcie_credit_fc_cmpl_data_posted;

	__le64	pcie_cmpl_longest;

	__le64	pcie_cmpl_shortest;

	__le64	cache_miss_count_cfcq;

	__le64	cache_miss_count_cfcs;

	__le64	cache_miss_count_cfcc;

	__le64	cache_miss_count_cfcm;

};



/* hwrm_fw_reset_input (size:192b/24B) */

struct hwrm_fw_reset_input {

	__le16	req_type;
@@ -9815,7 +9959,8 @@ struct hwrm_nvm_install_update_cmd_err { 
	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR           0x1UL

	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE           0x2UL

	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK      0x3UL

	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST         NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK

	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL

	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST              NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT

	u8	unused_0[7];

};