Commit acfdcaee authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "A bunch of clk driver fixes for issues found recently:

   - Fix the binding for versaclock3 that was introduced this merge
     window so we know what the values are for clk consumers

   - Fix a 64-bit division issue in the versaclock3 driver

   - Avoid breakage in the versaclock3 driver by rejiggering the enums
     used to layout clks

   - Fix the parent name of a clk in the Spreadtrum ums512 clk driver

   - Fix a suspend/resume issue in Skyworks Si521xx clk driver where
     regmap restoration fails because writes are wedged

   - Return zero from Tegra bpmp recalc_rate() implementation when an
     error occurs so we don't consider an error as a large rate"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: tegra: fix error return case for recalc_rate
  clk: si521xx: Fix regmap write accessor
  clk: si521xx: Use REGCACHE_FLAT instead of NONE
  clk: sprd: Fix thm_parents incorrect configuration
  clk: vc3: Make vc3_clk_mux enum values based on vc3_clk enum values
  clk: vc3: Fix output clock mapping
  clk: vc3: Fix 64 by 64 division
  dt-bindings: clock: versaclock3: Add description for #clock-cells property
parents 94b7ed38 a47b44fb

Documentation/devicetree/bindings/clock/renesas,5p35023.yaml

+7 −4
Original line number Diff line number Diff line
@@ -37,6 +37,9 @@ properties: 
    maxItems: 1



  '#clock-cells':

    description:

      The index in the assigned-clocks is mapped to the output clock as below

      0 - REF, 1 - SE1, 2 - SE2, 3 - SE3, 4 - DIFF1, 5 - DIFF2.

    const: 1



  clocks:
@@ -68,7 +71,7 @@ examples: 
            reg = <0x68>;

            #clock-cells = <1>;



            clocks = <&x1_x2>;

            clocks = <&x1>;



            renesas,settings = [

                80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
@@ -79,8 +82,8 @@ examples: 
            assigned-clocks = <&versa3 0>, <&versa3 1>,

                              <&versa3 2>, <&versa3 3>,

                              <&versa3 4>, <&versa3 5>;

            assigned-clock-rates = <12288000>, <25000000>,

                                   <12000000>, <11289600>,

                                   <11289600>, <24000000>;

            assigned-clock-rates = <24000000>, <11289600>,

                                   <11289600>, <12000000>,

                                   <25000000>, <12288000>;

        };

    };

drivers/clk/clk-si521xx.c

+5 −4
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ static int si521xx_regmap_i2c_write(void *context, unsigned int reg, 
				    unsigned int val)

{

	struct i2c_client *i2c = context;

	const u8 data[3] = { reg, 1, val };

	const u8 data[2] = { reg, val };

	const int count = ARRAY_SIZE(data);

	int ret;
@@ -146,7 +146,7 @@ static int si521xx_regmap_i2c_read(void *context, unsigned int reg, 
static const struct regmap_config si521xx_regmap_config = {

	.reg_bits = 8,

	.val_bits = 8,

	.cache_type = REGCACHE_NONE,

	.cache_type = REGCACHE_FLAT,

	.max_register = SI521XX_REG_DA,

	.rd_table = &si521xx_readable_table,

	.wr_table = &si521xx_writeable_table,
@@ -281,9 +281,10 @@ static int si521xx_probe(struct i2c_client *client) 
{

	const u16 chip_info = (u16)(uintptr_t)device_get_match_data(&client->dev);

	const struct clk_parent_data clk_parent_data = { .index = 0 };

	struct si521xx *si;

	const u8 data[3] = { SI521XX_REG_BC, 1, 1 };

	unsigned char name[6] = "DIFF0";

	struct clk_init_data init = {};

	struct si521xx *si;

	int i, ret;



	if (!chip_info)
@@ -308,7 +309,7 @@ static int si521xx_probe(struct i2c_client *client) 
				     "Failed to allocate register map\n");



	/* Always read back 1 Byte via I2C */

	ret = regmap_write(si->regmap, SI521XX_REG_BC, 1);

	ret = i2c_master_send(client, data, ARRAY_SIZE(data));

	if (ret < 0)

		return ret;

drivers/clk/clk-versaclock3.c

+40 −41
Original line number Diff line number Diff line
@@ -118,21 +118,21 @@ enum vc3_div { 
	VC3_DIV5,

};



enum vc3_clk_mux {

	VC3_DIFF2_MUX,

	VC3_DIFF1_MUX,

	VC3_SE3_MUX,

	VC3_SE2_MUX,

	VC3_SE1_MUX,

};



enum vc3_clk {

	VC3_DIFF2,

	VC3_DIFF1,

	VC3_SE3,

	VC3_SE2,

	VC3_SE1,

	VC3_REF,

	VC3_SE1,

	VC3_SE2,

	VC3_SE3,

	VC3_DIFF1,

	VC3_DIFF2,

};



enum vc3_clk_mux {

	VC3_SE1_MUX = VC3_SE1 - 1,

	VC3_SE2_MUX = VC3_SE2 - 1,

	VC3_SE3_MUX = VC3_SE3 - 1,

	VC3_DIFF1_MUX = VC3_DIFF1 - 1,

	VC3_DIFF2_MUX = VC3_DIFF2 - 1,

};



struct vc3_clk_data {
@@ -401,11 +401,10 @@ static long vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate, 
		/* Determine best fractional part, which is 16 bit wide */

		div_frc = rate % *parent_rate;

		div_frc *= BIT(16) - 1;

		do_div(div_frc, *parent_rate);



		vc3->div_frc = (u32)div_frc;

		vc3->div_frc = min_t(u64, div64_ul(div_frc, *parent_rate), U16_MAX);

		rate = (*parent_rate *

			(vc3->div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16);

			(vc3->div_int * VC3_2_POW_16 + vc3->div_frc) / VC3_2_POW_16);

	} else {

		rate = *parent_rate * vc3->div_int;

	}
@@ -897,33 +896,33 @@ static struct vc3_hw_data clk_div[] = { 
};



static struct vc3_hw_data clk_mux[] = {

	[VC3_DIFF2_MUX] = {

	[VC3_SE1_MUX] = {

		.data = &(struct vc3_clk_data) {

			.offs = VC3_DIFF2_CTRL_REG,

			.bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL

			.offs = VC3_SE1_DIV4_CTRL,

			.bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL

		},

		.hw.init = &(struct clk_init_data){

			.name = "diff2_mux",

			.name = "se1_mux",

			.ops = &vc3_clk_mux_ops,

			.parent_hws = (const struct clk_hw *[]) {

				&clk_div[VC3_DIV1].hw,

				&clk_div[VC3_DIV3].hw

				&clk_div[VC3_DIV5].hw,

				&clk_div[VC3_DIV4].hw

			},

			.num_parents = 2,

			.flags = CLK_SET_RATE_PARENT

		}

	},

	[VC3_DIFF1_MUX] = {

	[VC3_SE2_MUX] = {

		.data = &(struct vc3_clk_data) {

			.offs = VC3_DIFF1_CTRL_REG,

			.bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL

			.offs = VC3_SE2_CTRL_REG0,

			.bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL

		},

		.hw.init = &(struct clk_init_data){

			.name = "diff1_mux",

			.name = "se2_mux",

			.ops = &vc3_clk_mux_ops,

			.parent_hws = (const struct clk_hw *[]) {

				&clk_div[VC3_DIV1].hw,

				&clk_div[VC3_DIV3].hw

				&clk_div[VC3_DIV5].hw,

				&clk_div[VC3_DIV4].hw

			},

			.num_parents = 2,

			.flags = CLK_SET_RATE_PARENT
@@ -945,33 +944,33 @@ static struct vc3_hw_data clk_mux[] = { 
			.flags = CLK_SET_RATE_PARENT

		}

	},

	[VC3_SE2_MUX] = {

	[VC3_DIFF1_MUX] = {

		.data = &(struct vc3_clk_data) {

			.offs = VC3_SE2_CTRL_REG0,

			.bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL

			.offs = VC3_DIFF1_CTRL_REG,

			.bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL

		},

		.hw.init = &(struct clk_init_data){

			.name = "se2_mux",

			.name = "diff1_mux",

			.ops = &vc3_clk_mux_ops,

			.parent_hws = (const struct clk_hw *[]) {

				&clk_div[VC3_DIV5].hw,

				&clk_div[VC3_DIV4].hw

				&clk_div[VC3_DIV1].hw,

				&clk_div[VC3_DIV3].hw

			},

			.num_parents = 2,

			.flags = CLK_SET_RATE_PARENT

		}

	},

	[VC3_SE1_MUX] = {

	[VC3_DIFF2_MUX] = {

		.data = &(struct vc3_clk_data) {

			.offs = VC3_SE1_DIV4_CTRL,

			.bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL

			.offs = VC3_DIFF2_CTRL_REG,

			.bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL

		},

		.hw.init = &(struct clk_init_data){

			.name = "se1_mux",

			.name = "diff2_mux",

			.ops = &vc3_clk_mux_ops,

			.parent_hws = (const struct clk_hw *[]) {

				&clk_div[VC3_DIV5].hw,

				&clk_div[VC3_DIV4].hw

				&clk_div[VC3_DIV1].hw,

				&clk_div[VC3_DIV3].hw

			},

			.num_parents = 2,

			.flags = CLK_SET_RATE_PARENT
@@ -1110,7 +1109,7 @@ static int vc3_probe(struct i2c_client *client) 
				name, 0, CLK_SET_RATE_PARENT, 1, 1);

		else

			clk_out[i] = devm_clk_hw_register_fixed_factor_parent_hw(dev,

				name, &clk_mux[i].hw, CLK_SET_RATE_PARENT, 1, 1);

				name, &clk_mux[i - 1].hw, CLK_SET_RATE_PARENT, 1, 1);



		if (IS_ERR(clk_out[i]))

			return PTR_ERR(clk_out[i]);

drivers/clk/sprd/ums512-clk.c

+1 −1
Original line number Diff line number Diff line
@@ -800,7 +800,7 @@ static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_parents, 
			 0x250, 0, 3, UMS512_MUX_FLAG);



static const struct clk_parent_data thm_parents[] = {

	{ .fw_name = "ext-32m" },

	{ .fw_name = "ext-32k" },

	{ .hw = &clk_250k.hw  },

};

static SPRD_MUX_CLK_DATA(thm0_clk, "thm0-clk", thm_parents,

drivers/clk/tegra/clk-bpmp.c

+1 −1
Original line number Diff line number Diff line
@@ -159,7 +159,7 @@ static unsigned long tegra_bpmp_clk_recalc_rate(struct clk_hw *hw, 


	err = tegra_bpmp_clk_transfer(clk->bpmp, &msg);

	if (err < 0)

		return err;

		return 0;



	return response.rate;

}