Commit acdcfd94 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch irq/misc-5.15 into irq/irqchip-next 



* irq/misc-5.15:
  : .
  : Various irqchip fixes:
  :
  : - Fix edge interrupt support on loongson systems
  : - Advertise lack of wake-up logic on mtk-sysirq
  : - Fix mask tracking on the Apple AIC
  : - Correct priority reading of arm64 pseudo-NMI when SCR_EL3.FIQ==0
  : .
  irqchip/gic-v3: Fix priority comparison when non-secure priorities are used
  irqchip/apple-aic: Fix irq_disable from within irq handlers

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents cf39e60c 8d474dea

drivers/irqchip/irq-apple-aic.c

+1 −1
Original line number Diff line number Diff line
@@ -226,7 +226,7 @@ static void aic_irq_eoi(struct irq_data *d) 
	 * Reading the interrupt reason automatically acknowledges and masks

	 * the IRQ, so we just unmask it here if needed.

	 */

	if (!irqd_irq_disabled(d) && !irqd_irq_masked(d))

	if (!irqd_irq_masked(d))

		aic_irq_unmask(d);

}

drivers/irqchip/irq-gic-v3.c

+22 −1
Original line number Diff line number Diff line
@@ -100,6 +100,27 @@ EXPORT_SYMBOL(gic_pmr_sync); 
DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);

EXPORT_SYMBOL(gic_nonsecure_priorities);



/*

 * When the Non-secure world has access to group 0 interrupts (as a

 * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will

 * return the Distributor's view of the interrupt priority.

 *

 * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority

 * written by software is moved to the Non-secure range by the Distributor.

 *

 * If both are true (which is when gic_nonsecure_priorities gets enabled),

 * we need to shift down the priority programmed by software to match it

 * against the value returned by ICC_RPR_EL1.

 */

#define GICD_INT_RPR_PRI(priority)					\

	({								\

		u32 __priority = (priority);				\

		if (static_branch_unlikely(&gic_nonsecure_priorities))	\

			__priority = 0x80 | (__priority >> 1);		\

									\

		__priority;						\

	})



/* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */

static refcount_t *ppi_nmi_refs;
@@ -692,7 +713,7 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs 
		return;



	if (gic_supports_nmi() &&

	    unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) {

	    unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) {

		gic_handle_nmi(irqnr, regs);

		return;

	}