Commit accf5ef2 authored by Stefan Roese's avatar Stefan Roese Committed by Josh Boyer
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[POWERPC] 4xx: Add 440SPe revA runtime detection to PCIe 



This patch adds runtime detection of the 440SPe revision A chips. These
chips are equipped with a slighly different PCIe core and need special/
different initialization. The compatible node is changed to
"plb-pciex-440spe" ("A" and "B" dropped). This is needed for boards that
can be equipped with both PPC revisions like the AMCC Yucca.

Signed-off-by: default avatarStefan Roese <sr@denx.de>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarJosh Boyer <jwboyer@linux.vnet.ibm.com>
parent 25c24f3d

arch/powerpc/boot/dts/katmai.dts

+3 −3
Original line number Diff line number Diff line
@@ -267,7 +267,7 @@ 
			#interrupt-cells = <1>;

			#size-cells = <2>;

			#address-cells = <3>;

			compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";

			compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";

			primary;

			port = <0>; /* port number */

			reg = <d 00000000 20000000	/* Config space access */
@@ -308,7 +308,7 @@ 
			#interrupt-cells = <1>;

			#size-cells = <2>;

			#address-cells = <3>;

			compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";

			compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";

			primary;

			port = <1>; /* port number */

			reg = <d 20000000 20000000	/* Config space access */
@@ -349,7 +349,7 @@ 
			#interrupt-cells = <1>;

			#size-cells = <2>;

			#address-cells = <3>;

			compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";

			compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";

			primary;

			port = <2>; /* port number */

			reg = <d 40000000 20000000	/* Config space access */

arch/powerpc/sysdev/ppc4xx_pci.c

+17 −8
Original line number Diff line number Diff line
@@ -49,6 +49,15 @@ extern unsigned long total_memory; 
#define RES_TO_U32_HIGH(val)	(0)

#endif



static inline int ppc440spe_revA(void)

{

	/* Catch both 440SPe variants, with and without RAID6 support */

        if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)

                return 1;

        else

                return 0;

}



static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)

{

	struct pci_controller *hose;
@@ -516,8 +525,7 @@ static void __init ppc4xx_probe_pcix_bridge(struct device_node *np) 
 *

 * We support 3 parts currently based on the compatible property:

 *

 * ibm,plb-pciex-440speA

 * ibm,plb-pciex-440speB

 * ibm,plb-pciex-440spe

 * ibm,plb-pciex-405ex

 *

 * Anything else will be rejected for now as they are all subtly
@@ -688,7 +696,7 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 


	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);

	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);

	if (of_device_is_compatible(port->node, "ibm,plb-pciex-440speA"))

	if (ppc440spe_revA())

		mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);

	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);

	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
@@ -767,7 +775,6 @@ static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata = 
	.setup_utl	= ppc440speB_pciex_init_utl,

};





#endif /* CONFIG_44x */



#ifdef CONFIG_40x
@@ -881,10 +888,12 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np) 
		return 0;



#ifdef CONFIG_44x

	if (of_device_is_compatible(np, "ibm,plb-pciex-440speA"))

	if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {

		if (ppc440spe_revA())

			ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;

	else if (of_device_is_compatible(np, "ibm,plb-pciex-440speB"))

		else

			ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;

	}

#endif /* CONFIG_44x    */

#ifdef CONFIG_40x

	if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))