Commit accc3b4a authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 



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Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 510bbf82 511cce16

.mailmap

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@@ -71,6 +71,9 @@ Ben M Cahill <ben.m.cahill@intel.com> 
Ben Widawsky <bwidawsk@kernel.org> <ben@bwidawsk.net>

Ben Widawsky <bwidawsk@kernel.org> <ben.widawsky@intel.com>

Ben Widawsky <bwidawsk@kernel.org> <benjamin.widawsky@intel.com>

Bjorn Andersson <andersson@kernel.org> <bjorn@kryo.se>

Bjorn Andersson <andersson@kernel.org> <bjorn.andersson@linaro.org>

Bjorn Andersson <andersson@kernel.org> <bjorn.andersson@sonymobile.com>

Björn Steinbrink <B.Steinbrink@gmx.de>

Björn Töpel <bjorn@kernel.org> <bjorn.topel@gmail.com>

Björn Töpel <bjorn@kernel.org> <bjorn.topel@intel.com>

Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt

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@@ -34,8 +34,8 @@ Example: 
Use specific request line passing from dma

For example, MMC request line is 5



	sdhci: sdhci@98e00000 {

		compatible = "moxa,moxart-sdhci";

	mmc: mmc@98e00000 {

		compatible = "moxa,moxart-mmc";

		reg = <0x98e00000 0x5C>;

		interrupts = <5 0>;

		clocks = <&clk_apb>;

Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: i.MX8M DDR Controller



maintainers:

  - Leonard Crestez <leonard.crestez@nxp.com>

  - Peng Fan <peng.fan@nxp.com>



description:

  The DDRC block is integrated in i.MX8M for interfacing with DDR based

Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml

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@@ -40,6 +40,7 @@ properties: 
patternProperties:

  '^opp-?[0-9]+$':

    type: object

    additionalProperties: false



    properties:

      opp-hz: true

Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml

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@@ -19,6 +19,7 @@ properties: 
patternProperties:

  '^opp-?[0-9]+$':

    type: object

    additionalProperties: false



    properties:

      opp-level: true